Thien Dang Nguyen

Array ( [id] => 18881388 [patent_doc_number] => 20240004757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => ELECTRONIC DEVICE MANAGING CORRECTED ERROR AND OPERATING METHOD OF ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/295457 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19369154 [patent_doc_number] => 12061233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Method and circuit for performing error detection on a clock gated register signal [patent_app_type] => utility [patent_app_number] => 18/193509 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 16649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19485381 [patent_doc_number] => 20240333423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SYSTEMS AND METHODS OF INITIATING RETRANSMISSION REQUESTS [patent_app_type] => utility [patent_app_number] => 18/192239 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19487873 [patent_doc_number] => 12107605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-01 [patent_title] => Application-specific hardware device for decoding non-binary polar codes [patent_app_type] => utility [patent_app_number] => 18/126798 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 11213 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20214525 [patent_doc_number] => 12411171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Built-in self-test enhancements [patent_app_type] => utility [patent_app_number] => 18/189859 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5703 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19393594 [patent_doc_number] => 20240283464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => ROBUSTNESS WHEN USING APPLICATION LAYER FORWARD ERROR CORRECTION (AL-FEC) IN AN ATSC3 RECEIVER [patent_app_type] => utility [patent_app_number] => 18/186776 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19292673 [patent_doc_number] => 12032023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-09 [patent_title] => Bit-corrector circuits for photonic circuits with cascaded photonic gates [patent_app_type] => utility [patent_app_number] => 18/120308 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18813605 [patent_doc_number] => 20230387942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/180481 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19147274 [patent_doc_number] => 20240146330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SOFT DECISION-BASED LOW-COMPLEXITY DECODING METHOD AND COMPUTING DEVICE FOR PERFORMING THE METHOD [patent_app_type] => utility [patent_app_number] => 18/113756 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19275539 [patent_doc_number] => 12025662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-02 [patent_title] => Analog built-in self-test scheme for high volume power management integrated circuit products [patent_app_type] => utility [patent_app_number] => 18/113547 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19779971 [patent_doc_number] => 12229004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Grouping and error correction for non-volatile memory cells [patent_app_type] => utility [patent_app_number] => 18/106421 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3912 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18106421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925448 [patent_doc_number] => 20240028452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => FAULT-MITIGATING METHOD AND DATA PROCESSING CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/162601 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19796865 [patent_doc_number] => 12237846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Systems for error reduction of encoded data using neural networks [patent_app_type] => utility [patent_app_number] => 18/158332 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 23919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18158332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19327449 [patent_doc_number] => 12045132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Non-volatile memory device, controller for controlling the same, storage device having the same, and reading method thereof [patent_app_type] => utility [patent_app_number] => 18/156893 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 15849 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19506481 [patent_doc_number] => 12117901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Memory device, a controller for controlling the same, a memory system including the same, and an operating method of the same [patent_app_type] => utility [patent_app_number] => 18/096053 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 12149 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096053 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19283886 [patent_doc_number] => 20240220362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => Fast and Reliable Data Error Correction Methods and Apparatuses [patent_app_type] => utility [patent_app_number] => 18/092320 [patent_app_country] => US [patent_app_date] => 2023-01-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19625553 [patent_doc_number] => 12164382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Programmable IO module [patent_app_type] => utility [patent_app_number] => 18/059785 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 51 [patent_no_of_words] => 21742 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19275922 [patent_doc_number] => 12026050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => DDR DIMM, memory system and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/994324 [patent_app_country] => US [patent_app_date] => 2022-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19912370 [patent_doc_number] => 12288588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Memory, memory system and operation method of memory [patent_app_type] => utility [patent_app_number] => 17/994109 [patent_app_country] => US [patent_app_date] => 2022-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18359963 [patent_doc_number] => 20230141554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/053850 [patent_app_country] => US [patent_app_date] => 2022-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053850 [rel_patent_id] =>[rel_patent_doc_number] =>)