Search

Thienvu V. Tran

Supervisory Patent Examiner (ID: 7710, Phone: (571)270-1276 , Office: P/2836 )

Most Active Art Unit
2819
Art Unit(s)
2819, 2838, 2844, 2836, 2839
Total Applications
551
Issued Applications
466
Pending Applications
1
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8219425 [patent_doc_number] => 20120134199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'Magnetic Switching Cells and Methods of Making and Operating Same' [patent_app_type] => utility [patent_app_number] => 12/898548 [patent_app_country] => US [patent_app_date] => 2010-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 9564 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12898548 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/898548
Magnetic switching cells and methods of making and operating same Oct 4, 2010 Issued
Array ( [id] => 7556054 [patent_doc_number] => 08067957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'USB 2.0 HS voltage-mode transmitter with tuned termination resistance' [patent_app_type] => utility [patent_app_number] => 12/898640 [patent_app_country] => US [patent_app_date] => 2010-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3786 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/067/08067957.pdf [firstpage_image] =>[orig_patent_app_number] => 12898640 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/898640
USB 2.0 HS voltage-mode transmitter with tuned termination resistance Oct 4, 2010 Issued
Array ( [id] => 8625651 [patent_doc_number] => 08358148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-22 [patent_title] => 'Programmable integrated circuit and method of asynchronously routing data in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/896720 [patent_app_country] => US [patent_app_date] => 2010-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 36 [patent_no_of_words] => 19168 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12896720 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/896720
Programmable integrated circuit and method of asynchronously routing data in an integrated circuit Sep 30, 2010 Issued
Array ( [id] => 8091083 [patent_doc_number] => 20120081147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'APPARATUS AND METHOD FOR CONTROLLING SIGNAL DISTRIBUTION IN A SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/895388 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13019 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20120081147.pdf [firstpage_image] =>[orig_patent_app_number] => 12895388 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/895388
APPARATUS AND METHOD FOR CONTROLLING SIGNAL DISTRIBUTION IN A SEMICONDUCTOR INTEGRATED CIRCUIT Sep 29, 2010 Abandoned
Array ( [id] => 8550044 [patent_doc_number] => 08324930 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'Methods of implementing output ports and an integrated circuit having programmable output ports' [patent_app_type] => utility [patent_app_number] => 12/891578 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7957 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12891578 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/891578
Methods of implementing output ports and an integrated circuit having programmable output ports Sep 26, 2010 Issued
Array ( [id] => 9324291 [patent_doc_number] => 08659318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-25 [patent_title] => 'Systems and methods for implementing tristate signaling by using encapsulated unidirectional signals' [patent_app_type] => utility [patent_app_number] => 12/889735 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11288 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12889735 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/889735
Systems and methods for implementing tristate signaling by using encapsulated unidirectional signals Sep 23, 2010 Issued
Array ( [id] => 4473124 [patent_doc_number] => 07944230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-17 [patent_title] => 'Methodology and apparatus for reduction of soft errors in logic circuits' [patent_app_type] => utility [patent_app_number] => 12/882835 [patent_app_country] => US [patent_app_date] => 2010-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7641 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944230.pdf [firstpage_image] =>[orig_patent_app_number] => 12882835 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/882835
Methodology and apparatus for reduction of soft errors in logic circuits Sep 14, 2010 Issued
Array ( [id] => 6200198 [patent_doc_number] => 20110062984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Semiconductor device having plural unit buffers constituting output buffer' [patent_app_type] => utility [patent_app_number] => 12/923249 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20110062984.pdf [firstpage_image] =>[orig_patent_app_number] => 12923249 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923249
Semiconductor device having plural unit buffers constituting output buffer Sep 9, 2010 Issued
Array ( [id] => 7654719 [patent_doc_number] => 20110303988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'Semiconductor device and level shift circuit using the same' [patent_app_type] => utility [patent_app_number] => 12/923255 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5589 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20110303988.pdf [firstpage_image] =>[orig_patent_app_number] => 12923255 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923255
Semiconductor device and level shift circuit using the same Sep 9, 2010 Issued
Array ( [id] => 6200204 [patent_doc_number] => 20110062990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Semiconductor Device and Method of Controlling the Same' [patent_app_type] => utility [patent_app_number] => 12/871529 [patent_app_country] => US [patent_app_date] => 2010-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4222 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20110062990.pdf [firstpage_image] =>[orig_patent_app_number] => 12871529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/871529
Semiconductor device and method of controlling the same Aug 29, 2010 Issued
Array ( [id] => 7492888 [patent_doc_number] => 08030962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Configuration random access memory' [patent_app_type] => utility [patent_app_number] => 12/868575 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030962.pdf [firstpage_image] =>[orig_patent_app_number] => 12868575 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868575
Configuration random access memory Aug 24, 2010 Issued
Array ( [id] => 7782403 [patent_doc_number] => 20120043959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'Received Signal Strength Indicator and Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/861020 [patent_app_country] => US [patent_app_date] => 2010-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1868 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20120043959.pdf [firstpage_image] =>[orig_patent_app_number] => 12861020 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/861020
Received signal strength indicator and method thereof Aug 22, 2010 Issued
Array ( [id] => 8726294 [patent_doc_number] => 08405420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'System comprising a semiconductor device and structure' [patent_app_type] => utility [patent_app_number] => 12/859665 [patent_app_country] => US [patent_app_date] => 2010-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 276 [patent_figures_cnt] => 354 [patent_no_of_words] => 57529 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12859665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/859665
System comprising a semiconductor device and structure Aug 18, 2010 Issued
Array ( [id] => 8345127 [patent_doc_number] => 20120206054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'LED DRIVING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/391109 [patent_app_country] => US [patent_app_date] => 2010-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2337 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13391109 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/391109
LED driving circuit Aug 17, 2010 Issued
Array ( [id] => 6068401 [patent_doc_number] => 20110043250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'DRIVER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/858295 [patent_app_country] => US [patent_app_date] => 2010-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6211 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20110043250.pdf [firstpage_image] =>[orig_patent_app_number] => 12858295 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/858295
Driver circuit Aug 16, 2010 Issued
Array ( [id] => 7759804 [patent_doc_number] => 20120030449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'DATA TAG CONTROL FOR QUANTUM-DOT CELLULAR AUTOMATA' [patent_app_type] => utility [patent_app_number] => 12/847571 [patent_app_country] => US [patent_app_date] => 2010-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20120030449.pdf [firstpage_image] =>[orig_patent_app_number] => 12847571 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/847571
Data tag control for quantum-dot cellular automata Jul 29, 2010 Issued
Array ( [id] => 6419920 [patent_doc_number] => 20100277221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'Method for Solid State Thermal Electric Logic' [patent_app_type] => utility [patent_app_number] => 12/830122 [patent_app_country] => US [patent_app_date] => 2010-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3798 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20100277221.pdf [firstpage_image] =>[orig_patent_app_number] => 12830122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/830122
Method for solid state thermal electric logic Jul 1, 2010 Issued
Array ( [id] => 8550043 [patent_doc_number] => 08324929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'Integrated circuit with reconfigurable inputs/outputs' [patent_app_type] => utility [patent_app_number] => 12/826124 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12826124 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826124
Integrated circuit with reconfigurable inputs/outputs Jun 28, 2010 Issued
Array ( [id] => 4511935 [patent_doc_number] => 07915919 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-29 [patent_title] => 'Digital interface sensing apparatus' [patent_app_type] => utility [patent_app_number] => 12/824834 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1213 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915919.pdf [firstpage_image] =>[orig_patent_app_number] => 12824834 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/824834
Digital interface sensing apparatus Jun 27, 2010 Issued
Array ( [id] => 7541051 [patent_doc_number] => 08058897 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-15 [patent_title] => 'Configuration of a multi-die integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/825286 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9884 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/058/08058897.pdf [firstpage_image] =>[orig_patent_app_number] => 12825286 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/825286
Configuration of a multi-die integrated circuit Jun 27, 2010 Issued
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