
Thienvu V. Tran
Supervisory Patent Examiner (ID: 13310, Phone: (571)270-1276 , Office: P/2836 )
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2838, 2844, 2819, 2836, 2839 |
| Total Applications | 549 |
| Issued Applications | 464 |
| Pending Applications | 2 |
| Abandoned Applications | 88 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7667317
[patent_doc_number] => 20110316586
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-29
[patent_title] => 'LOW-VOLTAGE TO HIGH-VOLTAGE LEVEL TRANSLATION USING CAPACITIVE COUPLING'
[patent_app_type] => utility
[patent_app_number] => 12/823666
[patent_app_country] => US
[patent_app_date] => 2010-06-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/823666 | Low-voltage to high-voltage level translation using capacitive coupling | Jun 24, 2010 | Issued |
Array
(
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[patent_doc_number] => 08063661
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[patent_kind] => B2
[patent_issue_date] => 2011-11-22
[patent_title] => 'Semiconductor device having circuit blocks with mutually the same circuit configuration'
[patent_app_type] => utility
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Array
(
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[patent_doc_number] => 07982497
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[patent_kind] => B1
[patent_issue_date] => 2011-07-19
[patent_title] => 'Multiplexer-based interconnection network'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/819900 | Multiplexer-based interconnection network | Jun 20, 2010 | Issued |
Array
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[patent_doc_number] => 08098081
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[patent_kind] => B1
[patent_issue_date] => 2012-01-17
[patent_title] => 'Optimization of interconnection networks'
[patent_app_type] => utility
[patent_app_number] => 12/819903
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[firstpage_image] =>[orig_patent_app_number] => 12819903
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/819903 | Optimization of interconnection networks | Jun 20, 2010 | Issued |
Array
(
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[patent_doc_number] => 08115511
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[patent_issue_date] => 2012-02-14
[patent_title] => 'Method for fabrication of a semiconductor device and structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/797493 | Method for fabrication of a semiconductor device and structure | Jun 8, 2010 | Issued |
Array
(
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[patent_issue_date] => 2013-03-26
[patent_title] => 'Method and apparatus to serialize parallel data input values'
[patent_app_type] => utility
[patent_app_number] => 12/789566
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Array
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[patent_title] => 'Single-resistor static programming circuits and methods'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/799366 | Single-resistor static programming circuits and methods | Apr 22, 2010 | Issued |
Array
(
[id] => 7731238
[patent_doc_number] => 08102188
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[patent_issue_date] => 2012-01-24
[patent_title] => 'Method of and system for implementing a circuit in a device having programmable logic'
[patent_app_type] => utility
[patent_app_number] => 12/757770
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Array
(
[id] => 4518796
[patent_doc_number] => 07911231
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[patent_issue_date] => 2011-03-22
[patent_title] => 'Semiconductor integrated circuit device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/728388 | Semiconductor integrated circuit device | Mar 21, 2010 | Issued |
Array
(
[id] => 6324417
[patent_doc_number] => 20100244901
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[patent_issue_date] => 2010-09-30
[patent_title] => 'CLOCK SWITCHING CIRCUIT, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/726595
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/726595 | CLOCK SWITCHING CIRCUIT, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS | Mar 17, 2010 | Abandoned |
Array
(
[id] => 4614729
[patent_doc_number] => 07990173
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[patent_title] => 'Single event upset mitigation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/725324 | Single event upset mitigation | Mar 15, 2010 | Issued |
Array
(
[id] => 6200196
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/717442 | Semiconductor integrated circuit for reducing crosstalk | Mar 3, 2010 | Issued |
Array
(
[id] => 6282331
[patent_doc_number] => 20100156459
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[patent_title] => 'PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPERATURE'
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Array
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Array
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Array
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Array
(
[id] => 5501
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[patent_title] => 'USB 2.0 HS voltage-mode transmitter with tuned termination resistance'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/645236 | FPGA having a direct routing structure | Dec 21, 2009 | Issued |
Array
(
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[patent_title] => 'METHOD OF CONTROLLING A FLUORESCENT LAMP, A CONTROLLER AND A FLUORESCENT LAMP'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/634791 | Low latency, power-down safe level shifter | Dec 9, 2009 | Issued |