
Thienvu V. Tran
Supervisory Patent Examiner (ID: 7710, Phone: (571)270-1276 , Office: P/2836 )
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2838, 2844, 2836, 2839 |
| Total Applications | 551 |
| Issued Applications | 466 |
| Pending Applications | 1 |
| Abandoned Applications | 88 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8070935
[patent_doc_number] => 20110241556
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-06
[patent_title] => 'METHOD OF CONTROLLING A FLUORESCENT LAMP, A CONTROLLER AND A FLUORESCENT LAMP'
[patent_app_type] => utility
[patent_app_number] => 13/132628
[patent_app_country] => US
[patent_app_date] => 2009-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4373
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0241/20110241556.pdf
[firstpage_image] =>[orig_patent_app_number] => 13132628
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/132628 | METHOD OF CONTROLLING A FLUORESCENT LAMP, A CONTROLLER AND A FLUORESCENT LAMP | Dec 9, 2009 | Abandoned |
Array
(
[id] => 6344048
[patent_doc_number] => 20100085079
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-08
[patent_title] => 'Low Latency, Power-Down Safe Level Shifter'
[patent_app_type] => utility
[patent_app_number] => 12/634791
[patent_app_country] => US
[patent_app_date] => 2009-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6644
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20100085079.pdf
[firstpage_image] =>[orig_patent_app_number] => 12634791
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/634791 | Low latency, power-down safe level shifter | Dec 9, 2009 | Issued |
Array
(
[id] => 7481896
[patent_doc_number] => 20110234114
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-29
[patent_title] => 'AC LED LIGHTING ELEMENT AND AC LED LIGHTING SYSTEM METHODS AND APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/133122
[patent_app_country] => US
[patent_app_date] => 2009-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2633
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20110234114.pdf
[firstpage_image] =>[orig_patent_app_number] => 13133122
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/133122 | AC LED LIGHTING ELEMENT AND AC LED LIGHTING SYSTEM METHODS AND APPARATUS | Dec 6, 2009 | Abandoned |
Array
(
[id] => 8070945
[patent_doc_number] => 20110241552
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-06
[patent_title] => 'METHOD FOR MAXIMIZING THE PERFORMANCE OF A LUMINAIRE'
[patent_app_type] => utility
[patent_app_number] => 13/139065
[patent_app_country] => US
[patent_app_date] => 2009-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5481
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0241/20110241552.pdf
[firstpage_image] =>[orig_patent_app_number] => 13139065
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/139065 | METHOD FOR MAXIMIZING THE PERFORMANCE OF A LUMINAIRE | Dec 6, 2009 | Abandoned |
Array
(
[id] => 10883184
[patent_doc_number] => 08907567
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-09
[patent_title] => 'Plasma light source and plasma light generation method'
[patent_app_type] => utility
[patent_app_number] => 13/140789
[patent_app_country] => US
[patent_app_date] => 2009-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 7180
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13140789
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/140789 | Plasma light source and plasma light generation method | Dec 3, 2009 | Issued |
Array
(
[id] => 4466214
[patent_doc_number] => 07936186
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-05-03
[patent_title] => 'Method and apparatus for correcting duty cycle via current mode logic to CMOS converter'
[patent_app_type] => utility
[patent_app_number] => 12/631297
[patent_app_country] => US
[patent_app_date] => 2009-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 5525
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/936/07936186.pdf
[firstpage_image] =>[orig_patent_app_number] => 12631297
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/631297 | Method and apparatus for correcting duty cycle via current mode logic to CMOS converter | Dec 3, 2009 | Issued |
Array
(
[id] => 7481845
[patent_doc_number] => 20110234092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-29
[patent_title] => 'LED LIGHT SOURCE AND LAMP COMPRISING SUCH A LED LIGHT SOURCE'
[patent_app_type] => utility
[patent_app_number] => 13/139051
[patent_app_country] => US
[patent_app_date] => 2009-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2442
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20110234092.pdf
[firstpage_image] =>[orig_patent_app_number] => 13139051
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/139051 | LED light source and lamp comprising such a LED light source | Dec 2, 2009 | Issued |
Array
(
[id] => 4645116
[patent_doc_number] => 08022724
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-09-20
[patent_title] => 'Method and integrated circuit for secure reconfiguration of programmable logic'
[patent_app_type] => utility
[patent_app_number] => 12/625864
[patent_app_country] => US
[patent_app_date] => 2009-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4152
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/022/08022724.pdf
[firstpage_image] =>[orig_patent_app_number] => 12625864
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/625864 | Method and integrated circuit for secure reconfiguration of programmable logic | Nov 24, 2009 | Issued |
Array
(
[id] => 4436268
[patent_doc_number] => 07898296
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-03-01
[patent_title] => 'Distribution and synchronization of a divided clock signal'
[patent_app_type] => utility
[patent_app_number] => 12/624281
[patent_app_country] => US
[patent_app_date] => 2009-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5460
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/898/07898296.pdf
[firstpage_image] =>[orig_patent_app_number] => 12624281
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/624281 | Distribution and synchronization of a divided clock signal | Nov 22, 2009 | Issued |
Array
(
[id] => 6091543
[patent_doc_number] => 20110001514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-06
[patent_title] => 'COMMAND CONTROL CIRCUIT FOR SEMICONDUCTOR INTEGRATED DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/624144
[patent_app_country] => US
[patent_app_date] => 2009-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2681
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20110001514.pdf
[firstpage_image] =>[orig_patent_app_number] => 12624144
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/624144 | Command control circuit for semiconductor integrated device | Nov 22, 2009 | Issued |
Array
(
[id] => 9021217
[patent_doc_number] => 08531204
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-10
[patent_title] => 'Testable integrated circuit and test method therefor'
[patent_app_type] => utility
[patent_app_number] => 13/129107
[patent_app_country] => US
[patent_app_date] => 2009-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5711
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13129107
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/129107 | Testable integrated circuit and test method therefor | Nov 9, 2009 | Issued |
Array
(
[id] => 6217836
[patent_doc_number] => 20100053196
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-04
[patent_title] => 'PROGRAMMABLE CYCLE STATE MACHINE INTERFACE'
[patent_app_type] => utility
[patent_app_number] => 12/612020
[patent_app_country] => US
[patent_app_date] => 2009-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7853
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0053/20100053196.pdf
[firstpage_image] =>[orig_patent_app_number] => 12612020
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/612020 | PROGRAMMABLE CYCLE STATE MACHINE INTERFACE | Nov 3, 2009 | Abandoned |
Array
(
[id] => 4446726
[patent_doc_number] => 07864118
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-04
[patent_title] => 'Dual circularly polarized antenna system and a method of communicating signals by the antenna system'
[patent_app_type] => utility
[patent_app_number] => 12/612128
[patent_app_country] => US
[patent_app_date] => 2009-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4063
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/864/07864118.pdf
[firstpage_image] =>[orig_patent_app_number] => 12612128
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/612128 | Dual circularly polarized antenna system and a method of communicating signals by the antenna system | Nov 3, 2009 | Issued |
Array
(
[id] => 8956781
[patent_doc_number] => 08502563
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-06
[patent_title] => 'Non-binary decoder architecture and control signal logic for reduced circuit complexity'
[patent_app_type] => utility
[patent_app_number] => 13/127878
[patent_app_country] => US
[patent_app_date] => 2009-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4623
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13127878
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/127878 | Non-binary decoder architecture and control signal logic for reduced circuit complexity | Nov 3, 2009 | Issued |
Array
(
[id] => 7742319
[patent_doc_number] => 08106681
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-31
[patent_title] => 'Semiconductor device, and programming method and programming system therefor'
[patent_app_type] => utility
[patent_app_number] => 12/591015
[patent_app_country] => US
[patent_app_date] => 2009-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3954
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/106/08106681.pdf
[firstpage_image] =>[orig_patent_app_number] => 12591015
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/591015 | Semiconductor device, and programming method and programming system therefor | Nov 3, 2009 | Issued |
Array
(
[id] => 6522069
[patent_doc_number] => 20100123479
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-20
[patent_title] => 'LEVEL-SHIFT CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/612306
[patent_app_country] => US
[patent_app_date] => 2009-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5757
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0123/20100123479.pdf
[firstpage_image] =>[orig_patent_app_number] => 12612306
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/612306 | Level-shift circuit | Nov 3, 2009 | Issued |
Array
(
[id] => 6426171
[patent_doc_number] => 20100102850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-29
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/604910
[patent_app_country] => US
[patent_app_date] => 2009-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5317
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20100102850.pdf
[firstpage_image] =>[orig_patent_app_number] => 12604910
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/604910 | SEMICONDUCTOR DEVICE | Oct 22, 2009 | Abandoned |
Array
(
[id] => 7530998
[patent_doc_number] => 07843222
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-11-30
[patent_title] => 'Buffer-driving circuit capable of increasing responding speed and prolonging lifespan, buffer, and method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/582718
[patent_app_country] => US
[patent_app_date] => 2009-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5334
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 381
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/843/07843222.pdf
[firstpage_image] =>[orig_patent_app_number] => 12582718
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/582718 | Buffer-driving circuit capable of increasing responding speed and prolonging lifespan, buffer, and method thereof | Oct 20, 2009 | Issued |
Array
(
[id] => 7507293
[patent_doc_number] => 20110254457
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-20
[patent_title] => 'CIRCUIT FOR THE OPERATION OF AT LEAST ONE LED'
[patent_app_type] => utility
[patent_app_number] => 13/125791
[patent_app_country] => US
[patent_app_date] => 2009-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5479
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0254/20110254457.pdf
[firstpage_image] =>[orig_patent_app_number] => 13125791
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/125791 | Circuit for the operation of at least one LED | Oct 14, 2009 | Issued |
Array
(
[id] => 8859330
[patent_doc_number] => 08461871
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-11
[patent_title] => 'Interface circuit, analog flip-flop, and data processor'
[patent_app_type] => utility
[patent_app_number] => 13/122923
[patent_app_country] => US
[patent_app_date] => 2009-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 39
[patent_no_of_words] => 21084
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13122923
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/122923 | Interface circuit, analog flip-flop, and data processor | Oct 8, 2009 | Issued |