Search

Thienvu V. Tran

Supervisory Patent Examiner (ID: 17040, Phone: (571)270-1276 , Office: P/2836 )

Most Active Art Unit
2819
Art Unit(s)
2819, 2836, 2844, 2839, 2838
Total Applications
548
Issued Applications
464
Pending Applications
2
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5372067 [patent_doc_number] => 20090309627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'Methodology and Apparatus for Reduction of Soft Errors in Logic Circuits' [patent_app_type] => utility [patent_app_number] => 12/484708 [patent_app_country] => US [patent_app_date] => 2009-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20090309627.pdf [firstpage_image] =>[orig_patent_app_number] => 12484708 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/484708
Methodology and apparatus for reduction of soft errors in logic circuits Jun 14, 2009 Issued
Array ( [id] => 7551323 [patent_doc_number] => 08063657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Systems and devices for quantum processor architectures' [patent_app_type] => utility [patent_app_number] => 12/483971 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7827 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/063/08063657.pdf [firstpage_image] =>[orig_patent_app_number] => 12483971 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/483971
Systems and devices for quantum processor architectures Jun 11, 2009 Issued
Array ( [id] => 6568256 [patent_doc_number] => 20100060317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'DATA OUTPUT DEVICE AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/482075 [patent_app_country] => US [patent_app_date] => 2009-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3534 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20100060317.pdf [firstpage_image] =>[orig_patent_app_number] => 12482075 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/482075
Data output device and semiconductor memory apparatus including the same Jun 9, 2009 Issued
Array ( [id] => 5395546 [patent_doc_number] => 20090315609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'Level shift circuit and power semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/457283 [patent_app_country] => US [patent_app_date] => 2009-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5871 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315609.pdf [firstpage_image] =>[orig_patent_app_number] => 12457283 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/457283
Level shift circuit and power semiconductor device Jun 4, 2009 Issued
Array ( [id] => 5470531 [patent_doc_number] => 20090243697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'LEVEL SHIFT CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR CIRCUIT DEVICE HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/479221 [patent_app_country] => US [patent_app_date] => 2009-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8085 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243697.pdf [firstpage_image] =>[orig_patent_app_number] => 12479221 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479221
Level shift circuit, method for driving the same, and semiconductor circuit device having the same Jun 4, 2009 Issued
Array ( [id] => 4488772 [patent_doc_number] => 07902870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-08 [patent_title] => 'High speed level shifter circuit in advanced CMOS technology' [patent_app_type] => utility [patent_app_number] => 12/470943 [patent_app_country] => US [patent_app_date] => 2009-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4586 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902870.pdf [firstpage_image] =>[orig_patent_app_number] => 12470943 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/470943
High speed level shifter circuit in advanced CMOS technology May 21, 2009 Issued
Array ( [id] => 5488504 [patent_doc_number] => 20090289575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'Opto-Isolator Multi-Voltage Detection Circuit' [patent_app_type] => utility [patent_app_number] => 12/469940 [patent_app_country] => US [patent_app_date] => 2009-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4545 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20090289575.pdf [firstpage_image] =>[orig_patent_app_number] => 12469940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/469940
Opto-isolator multi-voltage detection circuit May 20, 2009 Issued
Array ( [id] => 7528081 [patent_doc_number] => 08044680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Semiconductor memory device and on-die termination circuit' [patent_app_type] => utility [patent_app_number] => 12/469446 [patent_app_country] => US [patent_app_date] => 2009-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5090 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/044/08044680.pdf [firstpage_image] =>[orig_patent_app_number] => 12469446 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/469446
Semiconductor memory device and on-die termination circuit May 19, 2009 Issued
Array ( [id] => 7546023 [patent_doc_number] => 08053997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Load control device having a trigger circuit characterized by a variable voltage threshold' [patent_app_type] => utility [patent_app_number] => 12/437859 [patent_app_country] => US [patent_app_date] => 2009-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6758 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/053/08053997.pdf [firstpage_image] =>[orig_patent_app_number] => 12437859 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/437859
Load control device having a trigger circuit characterized by a variable voltage threshold May 7, 2009 Issued
Array ( [id] => 7507517 [patent_doc_number] => 20110254588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'POWER SAVING CIRCUIT USING A CLOCK BUFFER AND MULTIPLE FLIP-FLOPS' [patent_app_type] => utility [patent_app_number] => 12/994115 [patent_app_country] => US [patent_app_date] => 2009-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2895 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20110254588.pdf [firstpage_image] =>[orig_patent_app_number] => 12994115 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/994115
Power saving circuit using a clock buffer and multiple flip-flops May 6, 2009 Issued
Array ( [id] => 6417480 [patent_doc_number] => 20100276815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'INTEGRATED CIRCUIT COMMUNICATION SYSTEM WITH DIFFERENTIAL SIGNAL AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/432162 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20100276815.pdf [firstpage_image] =>[orig_patent_app_number] => 12432162 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432162
Integrated circuit communication system with differential signal and method of manufacture thereof Apr 28, 2009 Issued
Array ( [id] => 6011464 [patent_doc_number] => 20110221470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'MAGNETIC DEVICE FOR PERFORMING A \"LOGIC FUNCTION\"' [patent_app_type] => utility [patent_app_number] => 12/988290 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 16921 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20110221470.pdf [firstpage_image] =>[orig_patent_app_number] => 12988290 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/988290
MAGNETIC DEVICE FOR PERFORMING A "LOGIC FUNCTION" Apr 14, 2009 Abandoned
Array ( [id] => 6068403 [patent_doc_number] => 20110043252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'SELF-TIMED TRIGGER WITH SINGLE-RAIL DATA INPUT' [patent_app_type] => utility [patent_app_number] => 12/937909 [patent_app_country] => US [patent_app_date] => 2009-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9910 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20110043252.pdf [firstpage_image] =>[orig_patent_app_number] => 12937909 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/937909
Self-timed trigger circuit with single-rail data input Apr 12, 2009 Issued
Array ( [id] => 55366 [patent_doc_number] => 07768293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-03 [patent_title] => 'Authentication for information provided to an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/421837 [patent_app_country] => US [patent_app_date] => 2009-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768293.pdf [firstpage_image] =>[orig_patent_app_number] => 12421837 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/421837
Authentication for information provided to an integrated circuit Apr 9, 2009 Issued
Array ( [id] => 7724810 [patent_doc_number] => 08098083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Apparatus and method for controlling delay stage of off-chip driver' [patent_app_type] => utility [patent_app_number] => 12/416929 [patent_app_country] => US [patent_app_date] => 2009-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1488 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/098/08098083.pdf [firstpage_image] =>[orig_patent_app_number] => 12416929 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/416929
Apparatus and method for controlling delay stage of off-chip driver Apr 1, 2009 Issued
Array ( [id] => 6324363 [patent_doc_number] => 20100244888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'METHOD AND APPARATUS FOR INCREASING SECURITY IN A SYSTEM USING AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/414752 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244888.pdf [firstpage_image] =>[orig_patent_app_number] => 12414752 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/414752
Method and apparatus for increasing security in a system using an integrated circuit Mar 30, 2009 Issued
Array ( [id] => 93532 [patent_doc_number] => 07737728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-15 [patent_title] => 'OCD driver slew rate control' [patent_app_type] => utility [patent_app_number] => 12/413603 [patent_app_country] => US [patent_app_date] => 2009-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1534 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/737/07737728.pdf [firstpage_image] =>[orig_patent_app_number] => 12413603 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/413603
OCD driver slew rate control Mar 29, 2009 Issued
Array ( [id] => 114290 [patent_doc_number] => 07714613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Level converter' [patent_app_type] => utility [patent_app_number] => 12/413746 [patent_app_country] => US [patent_app_date] => 2009-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5536 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/714/07714613.pdf [firstpage_image] =>[orig_patent_app_number] => 12413746 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/413746
Level converter Mar 29, 2009 Issued
Array ( [id] => 6323721 [patent_doc_number] => 20100244750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'HAND LANTERN' [patent_app_type] => utility [patent_app_number] => 12/413534 [patent_app_country] => US [patent_app_date] => 2009-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1630 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244750.pdf [firstpage_image] =>[orig_patent_app_number] => 12413534 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/413534
HAND LANTERN Mar 27, 2009 Abandoned
Array ( [id] => 5456434 [patent_doc_number] => 20090256586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'SEMICONDUCTOR DEVICE AND IMPEDANCE ADJUSTMENT METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 12/409838 [patent_app_country] => US [patent_app_date] => 2009-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6195 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20090256586.pdf [firstpage_image] =>[orig_patent_app_number] => 12409838 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/409838
Semiconductor device and impedance adjustment method of the same Mar 23, 2009 Issued
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