Search

Thienvu V. Tran

Supervisory Patent Examiner (ID: 13310, Phone: (571)270-1276 , Office: P/2836 )

Most Active Art Unit
2819
Art Unit(s)
2838, 2844, 2819, 2836, 2839
Total Applications
549
Issued Applications
464
Pending Applications
2
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5377835 [patent_doc_number] => 20090189674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'Circuit that facilitates proximity communication' [patent_app_type] => utility [patent_app_number] => 12/215943 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20090189674.pdf [firstpage_image] =>[orig_patent_app_number] => 12215943 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/215943
Circuit that facilitates proximity communication Jun 29, 2008 Issued
Array ( [id] => 4884441 [patent_doc_number] => 20080258773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'UNIVERSAL LOGIC GATE UTILIZING NANOTECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 12/143803 [patent_app_country] => US [patent_app_date] => 2008-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 17149 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20080258773.pdf [firstpage_image] =>[orig_patent_app_number] => 12143803 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143803
Universal logic gate utilizing nanotechnology Jun 21, 2008 Issued
Array ( [id] => 5512518 [patent_doc_number] => 20090212822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'BULK INPUT CURRENT SWITCH LOGIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/141112 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 5216 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20090212822.pdf [firstpage_image] =>[orig_patent_app_number] => 12141112 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141112
Bulk input current switch logic circuit Jun 17, 2008 Issued
Array ( [id] => 5512517 [patent_doc_number] => 20090212821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'BULK INPUT CURRENT SWITCH LOGIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/141111 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5852 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20090212821.pdf [firstpage_image] =>[orig_patent_app_number] => 12141111 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141111
Bulk input current switch logic circuit Jun 17, 2008 Issued
Array ( [id] => 25296 [patent_doc_number] => 07795910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Field-programmable gate array using charge-based nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 12/139664 [patent_app_country] => US [patent_app_date] => 2008-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 10039 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795910.pdf [firstpage_image] =>[orig_patent_app_number] => 12139664 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/139664
Field-programmable gate array using charge-based nonvolatile memory Jun 15, 2008 Issued
Array ( [id] => 5502 [patent_doc_number] => 07816943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Programmable cycle state machine interface' [patent_app_type] => utility [patent_app_number] => 12/139640 [patent_app_country] => US [patent_app_date] => 2008-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7888 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816943.pdf [firstpage_image] =>[orig_patent_app_number] => 12139640 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/139640
Programmable cycle state machine interface Jun 15, 2008 Issued
Array ( [id] => 5294292 [patent_doc_number] => 20090009218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Literal Gate Using Resonant Tunneling Diodes' [patent_app_type] => utility [patent_app_number] => 12/136250 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2318 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20090009218.pdf [firstpage_image] =>[orig_patent_app_number] => 12136250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136250
Literal Gate Using Resonant Tunneling Diodes Jun 9, 2008 Abandoned
Array ( [id] => 5365330 [patent_doc_number] => 20090302889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'INTEGRATED CIRCUIT CONTAINING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK' [patent_app_type] => utility [patent_app_number] => 12/135249 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302889.pdf [firstpage_image] =>[orig_patent_app_number] => 12135249 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135249
Integrated circuit containing multi-state restore circuitry for restoring state to a power-managed functional block Jun 8, 2008 Issued
Array ( [id] => 5365329 [patent_doc_number] => 20090302888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'INCREASED SENSITIVITY AND REDUCED OFFSET VARIATION IN HIGH DATA RATE HSSI RECEIVER' [patent_app_type] => utility [patent_app_number] => 12/134777 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4018 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302888.pdf [firstpage_image] =>[orig_patent_app_number] => 12134777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/134777
Increased sensitivity and reduced offset variation in high data rate HSSI receiver Jun 5, 2008 Issued
Array ( [id] => 4947420 [patent_doc_number] => 20080303546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS' [patent_app_type] => utility [patent_app_number] => 12/134451 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7629 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20080303546.pdf [firstpage_image] =>[orig_patent_app_number] => 12134451 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/134451
Dynamic impedance control for input/output buffers Jun 5, 2008 Issued
Array ( [id] => 240111 [patent_doc_number] => 07592831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Circuit to optimize charging of bootstrap capacitor with bootstrap diode emulator' [patent_app_type] => utility [patent_app_number] => 12/123842 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3145 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 426 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/592/07592831.pdf [firstpage_image] =>[orig_patent_app_number] => 12123842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/123842
Circuit to optimize charging of bootstrap capacitor with bootstrap diode emulator May 19, 2008 Issued
Array ( [id] => 4489881 [patent_doc_number] => 07884648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Pseudo-differential interfacing device having a switching circuit' [patent_app_type] => utility [patent_app_number] => 12/599114 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 12336 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884648.pdf [firstpage_image] =>[orig_patent_app_number] => 12599114 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/599114
Pseudo-differential interfacing device having a switching circuit May 19, 2008 Issued
Array ( [id] => 5263005 [patent_doc_number] => 20090115690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'GATE DRIVE CIRCUIT, DISPLAY SUBSTRATE HAVING THE SAME, AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/114882 [patent_app_country] => US [patent_app_date] => 2008-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6430 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20090115690.pdf [firstpage_image] =>[orig_patent_app_number] => 12114882 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/114882
Gate drive circuit, display substrate having the same, and method thereof May 4, 2008 Issued
Array ( [id] => 8364374 [patent_doc_number] => 08253442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Apparatus and method for signal transmission over a channel' [patent_app_type] => utility [patent_app_number] => 12/059065 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12059065 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/059065
Apparatus and method for signal transmission over a channel Mar 30, 2008 Issued
Array ( [id] => 4489809 [patent_doc_number] => 07884635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Integrated circuit, system and method including a performance test mode' [patent_app_type] => utility [patent_app_number] => 12/033483 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3768 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884635.pdf [firstpage_image] =>[orig_patent_app_number] => 12033483 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033483
Integrated circuit, system and method including a performance test mode Feb 18, 2008 Issued
Array ( [id] => 5389599 [patent_doc_number] => 20090206911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Solid State Thermal Electric Logic' [patent_app_type] => utility [patent_app_number] => 12/032549 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3754 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20090206911.pdf [firstpage_image] =>[orig_patent_app_number] => 12032549 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032549
Solid state thermal electric logic Feb 14, 2008 Issued
Array ( [id] => 243827 [patent_doc_number] => 07589564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Method of maintaining input and/or output configuration and data states during and when coming out of a low power mode' [patent_app_type] => utility [patent_app_number] => 12/030264 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4972 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589564.pdf [firstpage_image] =>[orig_patent_app_number] => 12030264 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030264
Method of maintaining input and/or output configuration and data states during and when coming out of a low power mode Feb 12, 2008 Issued
Array ( [id] => 278537 [patent_doc_number] => 07557615 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'High-speed serial data transmitter architecture' [patent_app_type] => utility [patent_app_number] => 12/069353 [patent_app_country] => US [patent_app_date] => 2008-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4312 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/557/07557615.pdf [firstpage_image] =>[orig_patent_app_number] => 12069353 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/069353
High-speed serial data transmitter architecture Feb 7, 2008 Issued
Array ( [id] => 44006 [patent_doc_number] => 07782084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-24 [patent_title] => 'Integrated circuit with reconfigurable inputs/outputs' [patent_app_type] => utility [patent_app_number] => 12/012672 [patent_app_country] => US [patent_app_date] => 2008-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5518 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782084.pdf [firstpage_image] =>[orig_patent_app_number] => 12012672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/012672
Integrated circuit with reconfigurable inputs/outputs Feb 3, 2008 Issued
Array ( [id] => 152821 [patent_doc_number] => 07683653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Process and circuit for improving the life duration of field-effect transistors' [patent_app_type] => utility [patent_app_number] => 12/024518 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683653.pdf [firstpage_image] =>[orig_patent_app_number] => 12024518 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024518
Process and circuit for improving the life duration of field-effect transistors Jan 31, 2008 Issued
Menu