
Thienvu V. Tran
Supervisory Patent Examiner (ID: 17040, Phone: (571)270-1276 , Office: P/2836 )
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2836, 2844, 2839, 2838 |
| Total Applications | 548 |
| Issued Applications | 464 |
| Pending Applications | 2 |
| Abandoned Applications | 87 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 243827
[patent_doc_number] => 07589564
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[patent_kind] => B2
[patent_issue_date] => 2009-09-15
[patent_title] => 'Method of maintaining input and/or output configuration and data states during and when coming out of a low power mode'
[patent_app_type] => utility
[patent_app_number] => 12/030264
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[pdf_file] => patents/07/589/07589564.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/030264 | Method of maintaining input and/or output configuration and data states during and when coming out of a low power mode | Feb 12, 2008 | Issued |
Array
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[patent_issue_date] => 2009-07-07
[patent_title] => 'High-speed serial data transmitter architecture'
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Array
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[patent_issue_date] => 2010-08-24
[patent_title] => 'Integrated circuit with reconfigurable inputs/outputs'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/012672 | Integrated circuit with reconfigurable inputs/outputs | Feb 3, 2008 | Issued |
Array
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[patent_issue_date] => 2010-03-23
[patent_title] => 'Process and circuit for improving the life duration of field-effect transistors'
[patent_app_type] => utility
[patent_app_number] => 12/024518
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[firstpage_image] =>[orig_patent_app_number] => 12024518
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/024518 | Process and circuit for improving the life duration of field-effect transistors | Jan 31, 2008 | Issued |
Array
(
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[patent_title] => 'Semiconductor integrated circuit device and storage apparatus having the same'
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Array
(
[id] => 236683
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[patent_issue_date] => 2009-09-29
[patent_title] => 'Clock gated circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/009903 | Clock gated circuit | Jan 22, 2008 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/010265 | Semiconductor device and method of fabricating the same | Jan 22, 2008 | Abandoned |
Array
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[patent_doc_number] => 20080238531
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[patent_title] => 'SYSTEMS, DEVICES, AND METHODS FOR CONTROLLABLY COUPLING QUBITS'
[patent_app_type] => utility
[patent_app_number] => 12/017995
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/017995 | SYSTEMS, DEVICES, AND METHODS FOR CONTROLLABLY COUPLING QUBITS | Jan 21, 2008 | Abandoned |
Array
(
[id] => 4696027
[patent_doc_number] => 20080218211
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[patent_issue_date] => 2008-09-11
[patent_title] => 'High-speed buffer circuit, system and method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/009144 | High-speed buffer circuit, system and method | Jan 14, 2008 | Issued |
Array
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[patent_title] => 'APPARATUS AND METHOD FOR CALIBRATING ON-DIE TERMINATION IN SEMICONDUCTOR MEMORY DEVICE'
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[patent_app_number] => 12/013804
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/013804 | Apparatus and method for calibrating on-die termination in semiconductor memory device | Jan 13, 2008 | Issued |
Array
(
[id] => 83172
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[patent_title] => 'Method of and system for implementing a circuit in a device having programmable logic'
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Array
(
[id] => 5579087
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[patent_title] => 'PECL/LVPECL input buffer that employs positive feedback to provide input hysteresis, symmetric headroom, and high noise immunity'
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/004766 | Reconfigurable array to compute digital algorithms | Dec 21, 2007 | Issued |
Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/944488 | Adjustable hold flip flop and method for adjusting hold requirements | Nov 22, 2007 | Issued |