Search

Thienvu V. Tran

Supervisory Patent Examiner (ID: 17040, Phone: (571)270-1276 , Office: P/2836 )

Most Active Art Unit
2819
Art Unit(s)
2819, 2836, 2844, 2839, 2838
Total Applications
548
Issued Applications
464
Pending Applications
2
Abandoned Applications
87

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 243827 [patent_doc_number] => 07589564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Method of maintaining input and/or output configuration and data states during and when coming out of a low power mode' [patent_app_type] => utility [patent_app_number] => 12/030264 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4972 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589564.pdf [firstpage_image] =>[orig_patent_app_number] => 12030264 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030264
Method of maintaining input and/or output configuration and data states during and when coming out of a low power mode Feb 12, 2008 Issued
Array ( [id] => 278537 [patent_doc_number] => 07557615 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'High-speed serial data transmitter architecture' [patent_app_type] => utility [patent_app_number] => 12/069353 [patent_app_country] => US [patent_app_date] => 2008-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4312 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/557/07557615.pdf [firstpage_image] =>[orig_patent_app_number] => 12069353 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/069353
High-speed serial data transmitter architecture Feb 7, 2008 Issued
Array ( [id] => 44006 [patent_doc_number] => 07782084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-24 [patent_title] => 'Integrated circuit with reconfigurable inputs/outputs' [patent_app_type] => utility [patent_app_number] => 12/012672 [patent_app_country] => US [patent_app_date] => 2008-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5518 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/782/07782084.pdf [firstpage_image] =>[orig_patent_app_number] => 12012672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/012672
Integrated circuit with reconfigurable inputs/outputs Feb 3, 2008 Issued
Array ( [id] => 152821 [patent_doc_number] => 07683653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Process and circuit for improving the life duration of field-effect transistors' [patent_app_type] => utility [patent_app_number] => 12/024518 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683653.pdf [firstpage_image] =>[orig_patent_app_number] => 12024518 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024518
Process and circuit for improving the life duration of field-effect transistors Jan 31, 2008 Issued
Array ( [id] => 5450325 [patent_doc_number] => 20090066361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'Semiconductor integrated circuit device and storage apparatus having the same' [patent_app_type] => utility [patent_app_number] => 12/010596 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10830 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20090066361.pdf [firstpage_image] =>[orig_patent_app_number] => 12010596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010596
Semiconductor integrated circuit device and storage apparatus having the same Jan 27, 2008 Issued
Array ( [id] => 236683 [patent_doc_number] => 07595665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Clock gated circuit' [patent_app_type] => utility [patent_app_number] => 12/009903 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4777 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595665.pdf [firstpage_image] =>[orig_patent_app_number] => 12009903 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/009903
Clock gated circuit Jan 22, 2008 Issued
Array ( [id] => 4843724 [patent_doc_number] => 20080180132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/010265 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3678 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20080180132.pdf [firstpage_image] =>[orig_patent_app_number] => 12010265 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/010265
Semiconductor device and method of fabricating the same Jan 22, 2008 Abandoned
Array ( [id] => 4716009 [patent_doc_number] => 20080238531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'SYSTEMS, DEVICES, AND METHODS FOR CONTROLLABLY COUPLING QUBITS' [patent_app_type] => utility [patent_app_number] => 12/017995 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6206 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20080238531.pdf [firstpage_image] =>[orig_patent_app_number] => 12017995 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/017995
SYSTEMS, DEVICES, AND METHODS FOR CONTROLLABLY COUPLING QUBITS Jan 21, 2008 Abandoned
Array ( [id] => 4696027 [patent_doc_number] => 20080218211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'High-speed buffer circuit, system and method' [patent_app_type] => utility [patent_app_number] => 12/009144 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3750 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20080218211.pdf [firstpage_image] =>[orig_patent_app_number] => 12009144 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/009144
High-speed buffer circuit, system and method Jan 14, 2008 Issued
Array ( [id] => 4662294 [patent_doc_number] => 20080253201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'APPARATUS AND METHOD FOR CALIBRATING ON-DIE TERMINATION IN SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/013804 [patent_app_country] => US [patent_app_date] => 2008-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20080253201.pdf [firstpage_image] =>[orig_patent_app_number] => 12013804 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/013804
Apparatus and method for calibrating on-die termination in semiconductor memory device Jan 13, 2008 Issued
Array ( [id] => 83172 [patent_doc_number] => 07746099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-29 [patent_title] => 'Method of and system for implementing a circuit in a device having programmable logic' [patent_app_type] => utility [patent_app_number] => 12/008489 [patent_app_country] => US [patent_app_date] => 2008-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7233 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746099.pdf [firstpage_image] =>[orig_patent_app_number] => 12008489 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/008489
Method of and system for implementing a circuit in a device having programmable logic Jan 10, 2008 Issued
Array ( [id] => 5579087 [patent_doc_number] => 20090174433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'PECL/LVPECL input buffer that employs positive feedback to provide input hysteresis, symmetric headroom, and high noise immunity' [patent_app_type] => utility [patent_app_number] => 12/008133 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7573 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20090174433.pdf [firstpage_image] =>[orig_patent_app_number] => 12008133 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/008133
PECL/LVPECL input buffer that employs positive feedback to provide input hysteresis, symmetric headroom, and high noise immunity Jan 7, 2008 Issued
Array ( [id] => 7592701 [patent_doc_number] => 07652501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Programmable logic device structure using third dimensional memory' [patent_app_type] => utility [patent_app_number] => 12/008077 [patent_app_country] => US [patent_app_date] => 2008-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5014 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/652/07652501.pdf [firstpage_image] =>[orig_patent_app_number] => 12008077 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/008077
Programmable logic device structure using third dimensional memory Jan 6, 2008 Issued
Array ( [id] => 5347729 [patent_doc_number] => 20090003090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Impedance adjusting circuit and semiconductor memory device having the same' [patent_app_type] => utility [patent_app_number] => 12/006112 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20090003090.pdf [firstpage_image] =>[orig_patent_app_number] => 12006112 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/006112
Impedance adjusting circuit and semiconductor memory device having the same Dec 30, 2007 Issued
Array ( [id] => 4584531 [patent_doc_number] => 07834660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'State machines using resistivity-sensitive memories' [patent_app_type] => utility [patent_app_number] => 12/006199 [patent_app_country] => US [patent_app_date] => 2007-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5237 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/834/07834660.pdf [firstpage_image] =>[orig_patent_app_number] => 12006199 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/006199
State machines using resistivity-sensitive memories Dec 29, 2007 Issued
Array ( [id] => 7530991 [patent_doc_number] => 07843215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Reconfigurable array to compute digital algorithms' [patent_app_type] => utility [patent_app_number] => 12/004766 [patent_app_country] => US [patent_app_date] => 2007-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5888 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/843/07843215.pdf [firstpage_image] =>[orig_patent_app_number] => 12004766 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/004766
Reconfigurable array to compute digital algorithms Dec 21, 2007 Issued
Array ( [id] => 4724539 [patent_doc_number] => 20080204080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Mobile circuit robust against input voltage change' [patent_app_type] => utility [patent_app_number] => 12/004739 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20080204080.pdf [firstpage_image] =>[orig_patent_app_number] => 12004739 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/004739
Mobile circuit robust against input voltage change Dec 20, 2007 Abandoned
Array ( [id] => 93528 [patent_doc_number] => 07733121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Methods and apparatus for programmably powering down structured application-specific integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/999269 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6060 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/733/07733121.pdf [firstpage_image] =>[orig_patent_app_number] => 11999269 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/999269
Methods and apparatus for programmably powering down structured application-specific integrated circuits Dec 2, 2007 Issued
Array ( [id] => 5573411 [patent_doc_number] => 20090140772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES' [patent_app_type] => utility [patent_app_number] => 11/946876 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4126 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20090140772.pdf [firstpage_image] =>[orig_patent_app_number] => 11946876 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/946876
Architecture for VBUS pulsing in UDSM processes Nov 28, 2007 Issued
Array ( [id] => 5562060 [patent_doc_number] => 20090134912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS' [patent_app_type] => utility [patent_app_number] => 11/944488 [patent_app_country] => US [patent_app_date] => 2007-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3842 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20090134912.pdf [firstpage_image] =>[orig_patent_app_number] => 11944488 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/944488
Adjustable hold flip flop and method for adjusting hold requirements Nov 22, 2007 Issued
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