Search

Thienvu V. Tran

Supervisory Patent Examiner (ID: 7710, Phone: (571)270-1276 , Office: P/2836 )

Most Active Art Unit
2819
Art Unit(s)
2819, 2838, 2844, 2836, 2839
Total Applications
551
Issued Applications
466
Pending Applications
1
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7592698 [patent_doc_number] => 07652504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Low latency, power-down safe level shifter' [patent_app_type] => utility [patent_app_number] => 11/610236 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6624 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/652/07652504.pdf [firstpage_image] =>[orig_patent_app_number] => 11610236 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/610236
Low latency, power-down safe level shifter Dec 12, 2006 Issued
Array ( [id] => 7599344 [patent_doc_number] => 07583104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Maintaining input and/or output configuration and data state during and when coming out of a low power mode' [patent_app_type] => utility [patent_app_number] => 11/609610 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4902 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/583/07583104.pdf [firstpage_image] =>[orig_patent_app_number] => 11609610 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/609610
Maintaining input and/or output configuration and data state during and when coming out of a low power mode Dec 11, 2006 Issued
Array ( [id] => 4783119 [patent_doc_number] => 20080136448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'STATE MACHINE AND SYSTEM AND METHOD OF IMPLEMENTING A STATE MACHINE' [patent_app_type] => utility [patent_app_number] => 11/608558 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 17709 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20080136448.pdf [firstpage_image] =>[orig_patent_app_number] => 11608558 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608558
State machine and system and method of implementing a state machine Dec 7, 2006 Issued
Array ( [id] => 4783114 [patent_doc_number] => 20080136443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Input Termination For Delay Locked Loop Feedback With Impedance Matching' [patent_app_type] => utility [patent_app_number] => 11/608234 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8208 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20080136443.pdf [firstpage_image] =>[orig_patent_app_number] => 11608234 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608234
Input termination for delay locked loop feedback with impedance matching Dec 6, 2006 Issued
Array ( [id] => 282354 [patent_doc_number] => 07554355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Crossbar switch architecture for multi-processor SoC platform' [patent_app_type] => utility [patent_app_number] => 11/607515 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4978 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554355.pdf [firstpage_image] =>[orig_patent_app_number] => 11607515 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/607515
Crossbar switch architecture for multi-processor SoC platform Nov 30, 2006 Issued
Array ( [id] => 587585 [patent_doc_number] => 07449917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Level shifting circuit for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/606243 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5598 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/449/07449917.pdf [firstpage_image] =>[orig_patent_app_number] => 11606243 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/606243
Level shifting circuit for semiconductor device Nov 29, 2006 Issued
Array ( [id] => 5116794 [patent_doc_number] => 20070138508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Mobile-Based Delayed Flip-Flop Circuit with NRZ-Mode Output' [patent_app_type] => utility [patent_app_number] => 11/565011 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1672 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138508.pdf [firstpage_image] =>[orig_patent_app_number] => 11565011 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565011
Mobile-Based Delayed Flip-Flop Circuit with NRZ-Mode Output Nov 29, 2006 Abandoned
Array ( [id] => 5067096 [patent_doc_number] => 20070188197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Flip-flop circuit and frequency divider using the flip-flop circuit' [patent_app_type] => utility [patent_app_number] => 11/605226 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8502 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20070188197.pdf [firstpage_image] =>[orig_patent_app_number] => 11605226 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605226
Flip-flop circuit and frequency divider using the flip-flop circuit Nov 28, 2006 Issued
Array ( [id] => 560031 [patent_doc_number] => 07468617 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-23 [patent_title] => 'Electrostatic discharge (ESD) protection device for use with multiple I/O standards' [patent_app_type] => utility [patent_app_number] => 11/605516 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3988 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/468/07468617.pdf [firstpage_image] =>[orig_patent_app_number] => 11605516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605516
Electrostatic discharge (ESD) protection device for use with multiple I/O standards Nov 27, 2006 Issued
Array ( [id] => 5251025 [patent_doc_number] => 20070132481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Programmable Josephson voltage standard device employing microwave driving of multiple frequencies' [patent_app_type] => utility [patent_app_number] => 11/604230 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3318 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20070132481.pdf [firstpage_image] =>[orig_patent_app_number] => 11604230 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/604230
Programmable Josephson voltage standard device employing microwave driving of multiple frequencies Nov 26, 2006 Issued
Array ( [id] => 5077355 [patent_doc_number] => 20070120579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Integrated circuit device and electronic instrument' [patent_app_type] => utility [patent_app_number] => 11/603746 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20070120579.pdf [firstpage_image] =>[orig_patent_app_number] => 11603746 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/603746
Integrated circuit device and electronic instrument Nov 21, 2006 Issued
Array ( [id] => 5094143 [patent_doc_number] => 20070115752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Output Driver and Output Driving Method for Enhancing Initial Output Data Using Timing' [patent_app_type] => utility [patent_app_number] => 11/561765 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2501 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20070115752.pdf [firstpage_image] =>[orig_patent_app_number] => 11561765 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561765
Output driver and output driving method for enhancing initial output data using timing Nov 19, 2006 Issued
Array ( [id] => 5099196 [patent_doc_number] => 20070182456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Reducing Pin Count When the Digital Output is to be Provided in Differential or Single-ended Form' [patent_app_type] => utility [patent_app_number] => 11/561424 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2598 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20070182456.pdf [firstpage_image] =>[orig_patent_app_number] => 11561424 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561424
Reducing Pin Count When the Digital Output is to be Provided in Differential or Single-ended Form Nov 19, 2006 Abandoned
Array ( [id] => 807600 [patent_doc_number] => 07420394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'Latching input buffer circuit with variable hysteresis' [patent_app_type] => utility [patent_app_number] => 11/561209 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3463 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/420/07420394.pdf [firstpage_image] =>[orig_patent_app_number] => 11561209 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561209
Latching input buffer circuit with variable hysteresis Nov 16, 2006 Issued
Array ( [id] => 4897325 [patent_doc_number] => 20080116938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'Hybrid Keeper Circuit for Dynamic Logic' [patent_app_type] => utility [patent_app_number] => 11/560440 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20080116938.pdf [firstpage_image] =>[orig_patent_app_number] => 11560440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560440
Hybrid Keeper Circuit for Dynamic Logic Nov 15, 2006 Abandoned
Array ( [id] => 113163 [patent_doc_number] => 07719313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Versatile and compact DC-coupled CML buffer' [patent_app_type] => utility [patent_app_number] => 11/560737 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5439 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/719/07719313.pdf [firstpage_image] =>[orig_patent_app_number] => 11560737 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560737
Versatile and compact DC-coupled CML buffer Nov 15, 2006 Issued
Array ( [id] => 8340872 [patent_doc_number] => 08242801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Semiconductor body, circuit arrangement having the semiconductor body and method' [patent_app_type] => utility [patent_app_number] => 12/085557 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7003 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12085557 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/085557
Semiconductor body, circuit arrangement having the semiconductor body and method Nov 15, 2006 Issued
Array ( [id] => 4902203 [patent_doc_number] => 20080111616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'COMPENSATION FOR LEAKAGE CURRENT VARIATION BY THE UTILIZATION OF AN AUTOMATIC SELF-ADAPTIVE KEEPER' [patent_app_type] => utility [patent_app_number] => 11/559289 [patent_app_country] => US [patent_app_date] => 2006-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3860 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20080111616.pdf [firstpage_image] =>[orig_patent_app_number] => 11559289 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559289
Compensation for leakage current from dynamic storage node variation by the utilization of an automatic self-adaptive keeper Nov 12, 2006 Issued
Array ( [id] => 576040 [patent_doc_number] => 07463065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-09 [patent_title] => 'Low power single-rail-input voltage level shifter' [patent_app_type] => utility [patent_app_number] => 11/559155 [patent_app_country] => US [patent_app_date] => 2006-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5607 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 598 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463065.pdf [firstpage_image] =>[orig_patent_app_number] => 11559155 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559155
Low power single-rail-input voltage level shifter Nov 12, 2006 Issued
Array ( [id] => 240120 [patent_doc_number] => 07592840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Domino circuit with disable feature' [patent_app_type] => utility [patent_app_number] => 11/557913 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2045 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/592/07592840.pdf [firstpage_image] =>[orig_patent_app_number] => 11557913 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/557913
Domino circuit with disable feature Nov 7, 2006 Issued
Menu