Search

Thinh T. Nguyen

Examiner (ID: 17352, Phone: (571)272-1790 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2818
Total Applications
2487
Issued Applications
2130
Pending Applications
85
Abandoned Applications
277

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17115885 [patent_doc_number] => 20210296482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => STRUCTURES AND METHODS FOR SOURCE-DOWN VERTICAL SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/948880 [patent_app_country] => US [patent_app_date] => 2020-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948880 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/948880
Structures and methods for source-down vertical semiconductor device Oct 4, 2020 Issued
Array ( [id] => 16586180 [patent_doc_number] => 20210020582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/060082 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/060082
Semiconductor structure and fabrication method thereof Sep 30, 2020 Issued
Array ( [id] => 16578811 [patent_doc_number] => 20210013212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING SPACER [patent_app_type] => utility [patent_app_number] => 17/037851 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037851 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037851
Method of manufacturing semiconductor device including spacer Sep 29, 2020 Issued
Array ( [id] => 16796139 [patent_doc_number] => 20210125956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/038682 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038682 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/038682
Display device and method of manufacturing the same Sep 29, 2020 Issued
Array ( [id] => 17284128 [patent_doc_number] => 11201170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Three-dimensional semiconductor memory device and manufacturing method of the three-dimensional semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/031046 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 29 [patent_no_of_words] => 10412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031046
Three-dimensional semiconductor memory device and manufacturing method of the three-dimensional semiconductor memory device Sep 23, 2020 Issued
Array ( [id] => 16731296 [patent_doc_number] => 20210098444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => ISOLATION TRENCHES FOR ESD CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/028732 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028732
Isolation trenches for ESD circuits Sep 21, 2020 Issued
Array ( [id] => 17270487 [patent_doc_number] => 11195918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-07 [patent_title] => Structure of semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/026062 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4037 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026062 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026062
Structure of semiconductor device and method for fabricating the same Sep 17, 2020 Issued
Array ( [id] => 16545134 [patent_doc_number] => 20200411549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/018179 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018179
Vertical memory devices and methods of manufacturing the same Sep 10, 2020 Issued
Array ( [id] => 17517024 [patent_doc_number] => 11296185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Isolator [patent_app_type] => utility [patent_app_number] => 17/014306 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 44 [patent_no_of_words] => 10453 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/014306
Isolator Sep 7, 2020 Issued
Array ( [id] => 17239614 [patent_doc_number] => 11183506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Method of making embedded memory device with silicon-on-insulator substrate [patent_app_type] => utility [patent_app_number] => 17/005139 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 61 [patent_no_of_words] => 3612 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17005139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/005139
Method of making embedded memory device with silicon-on-insulator substrate Aug 26, 2020 Issued
Array ( [id] => 16515688 [patent_doc_number] => 20200394946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => Chip-on-Film and Display Including the Same [patent_app_type] => utility [patent_app_number] => 17/004657 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004657
Chip-on-film and display including the same Aug 26, 2020 Issued
Array ( [id] => 17166282 [patent_doc_number] => 11152394 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-19 [patent_title] => Structure with polycrystalline isolation region below polycrystalline fill shape(s) and selective active device(s), and related method [patent_app_type] => utility [patent_app_number] => 16/992445 [patent_app_country] => US [patent_app_date] => 2020-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6170 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16992445 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/992445
Structure with polycrystalline isolation region below polycrystalline fill shape(s) and selective active device(s), and related method Aug 12, 2020 Issued
Array ( [id] => 17574301 [patent_doc_number] => 11322576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Inductive device [patent_app_type] => utility [patent_app_number] => 16/947359 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947359 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947359
Inductive device Jul 28, 2020 Issued
Array ( [id] => 17347211 [patent_doc_number] => 20220013542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => SEMICONDUCTOR DEVICE HAVING BURIED BIAS PADS [patent_app_type] => utility [patent_app_number] => 16/936030 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936030 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936030
Semiconductor device having buried bias pads Jul 21, 2020 Issued
Array ( [id] => 17971431 [patent_doc_number] => 11488981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Array of vertical transistors and method used in forming an array of vertical transistors [patent_app_type] => utility [patent_app_number] => 16/934607 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 35 [patent_no_of_words] => 6061 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934607 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/934607
Array of vertical transistors and method used in forming an array of vertical transistors Jul 20, 2020 Issued
Array ( [id] => 16425235 [patent_doc_number] => 20200350433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => Stress Modulation for Dielectric Layers [patent_app_type] => utility [patent_app_number] => 16/933622 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933622 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933622
Stress modulation for dielectric layers Jul 19, 2020 Issued
Array ( [id] => 16424956 [patent_doc_number] => 20200350154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => METHODS OF MANUFACTURING ENGINEERED SUBSTRATE STRUCTURES FOR POWER AND RF APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/931049 [patent_app_country] => US [patent_app_date] => 2020-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931049 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/931049
Methods of manufacturing engineered substrate structures for power and RF applications Jul 15, 2020 Issued
Array ( [id] => 18528686 [patent_doc_number] => 11715689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Method of forming metal interconnection [patent_app_type] => utility [patent_app_number] => 16/927328 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927328 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927328
Method of forming metal interconnection Jul 12, 2020 Issued
Array ( [id] => 17122128 [patent_doc_number] => 11133270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-28 [patent_title] => Integrated circuit device and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 16/914482 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3012 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914482 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914482
Integrated circuit device and fabrication method thereof Jun 28, 2020 Issued
Array ( [id] => 16541218 [patent_doc_number] => 20200407631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => CADMIUM-FREE QUANTUM DOTS, AND COMPOSITE AND DISPLAY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/914598 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914598 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914598
Cadmium-free quantum dots, and composite and display device including the same Jun 28, 2020 Issued
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