Search

Thinh T. Nguyen

Examiner (ID: 17352, Phone: (571)272-1790 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2818
Total Applications
2487
Issued Applications
2130
Pending Applications
85
Abandoned Applications
277

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15857555 [patent_doc_number] => 10644079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Organic light emitting diode display [patent_app_type] => utility [patent_app_number] => 16/105361 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105361 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105361
Organic light emitting diode display Aug 19, 2018 Issued
Array ( [id] => 16456386 [patent_doc_number] => 20200365812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => ORGANIC ELECTROLUMINESCENCE ELEMENT AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/640412 [patent_app_country] => US [patent_app_date] => 2018-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 494 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16640412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/640412
Organic electroluminescence element and electronic device Aug 16, 2018 Issued
Array ( [id] => 13629891 [patent_doc_number] => 20180366498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => ARRAY SUBSTRATE MANUFACTURING METHOD AND ARRAY SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/101534 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 455 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16101534 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/101534
Array substrate manufacturing method and array substrate Aug 12, 2018 Issued
Array ( [id] => 15857245 [patent_doc_number] => 10643919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Fan-out semiconductor package [patent_app_type] => utility [patent_app_number] => 16/057023 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 11690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057023 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057023
Fan-out semiconductor package Aug 6, 2018 Issued
Array ( [id] => 14920659 [patent_doc_number] => 10431657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-01 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/056917 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056917 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056917
Semiconductor device Aug 6, 2018 Issued
Array ( [id] => 14859429 [patent_doc_number] => 10418451 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-17 [patent_title] => Split-gate flash memory cell with varying insulation gate oxides, and method of forming same [patent_app_type] => utility [patent_app_number] => 16/057750 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 3207 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057750 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057750
Split-gate flash memory cell with varying insulation gate oxides, and method of forming same Aug 6, 2018 Issued
Array ( [id] => 13963273 [patent_doc_number] => 20190057981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => CO-INTEGRATION OF BULK AND SOI TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/057466 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057466 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057466
Co-integration of bulk and SOI transistors Aug 6, 2018 Issued
Array ( [id] => 13936197 [patent_doc_number] => 20190051614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => SEMICONDUCTOR PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING [patent_app_type] => utility [patent_app_number] => 16/057773 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057773 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057773
Semiconductor packages with electromagnetic interference shielding Aug 6, 2018 Issued
Array ( [id] => 14191179 [patent_doc_number] => 20190115295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/057724 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 423 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057724 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057724
High speed semiconductor device with noise reduction wiring pattern Aug 6, 2018 Issued
Array ( [id] => 16148169 [patent_doc_number] => 10707161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Cavity wall structure for semiconductor packaging [patent_app_type] => utility [patent_app_number] => 16/056541 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056541 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056541
Cavity wall structure for semiconductor packaging Aug 6, 2018 Issued
Array ( [id] => 15331643 [patent_doc_number] => 20200006151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => Forming Nitrogen-Containing Low-K Gate Spacer [patent_app_type] => utility [patent_app_number] => 16/057308 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057308 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057308
Forming nitrogen-containing low-K gate spacer Aug 6, 2018 Issued
Array ( [id] => 14350529 [patent_doc_number] => 20190157237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => SEMICONDUCTOR DEVICES HAVING WIRE BONDING STRUCTURES AND METHODS OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/057323 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057323
SEMICONDUCTOR DEVICES HAVING WIRE BONDING STRUCTURES AND METHODS OF FABRICATING THE SAME Aug 6, 2018 Abandoned
Array ( [id] => 14475807 [patent_doc_number] => 20190189551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR MODULE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/056651 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056651 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056651
Semiconductor package and semiconductor module including the same Aug 6, 2018 Issued
Array ( [id] => 15123587 [patent_doc_number] => 20190348427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => Method of Making Embedded Memory Device With Silicon-On-Insulator Substrate [patent_app_type] => utility [patent_app_number] => 16/057749 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057749
Method of making embedded memory device with silicon-on-insulator substrate Aug 6, 2018 Issued
Array ( [id] => 14859491 [patent_doc_number] => 10418482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => High voltage device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/057725 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 38 [patent_no_of_words] => 8694 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 446 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057725 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057725
High voltage device and manufacturing method thereof Aug 6, 2018 Issued
Array ( [id] => 15955317 [patent_doc_number] => 10665574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/056709 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6925 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056709 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056709
Semiconductor package Aug 6, 2018 Issued
Array ( [id] => 13932225 [patent_doc_number] => 20190049628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => STRUCTURE HAVING LOW REFLECTANCE SURFACE AND METHOD FOR MANUFACTURING THE STRUCTURE, AND SOLAR CELL AND OPTICAL FILM HAVING THE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/057128 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057128 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057128
Structure having low reflectance surface and method for manufacturing the structure, and solar cell and optical film having the structure Aug 6, 2018 Issued
Array ( [id] => 13936251 [patent_doc_number] => 20190051641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => LOGIC DRIVE BASED ON STANDARDIZED COMMODITY PROGRAMMABLE LOGIC SEMICONDUCTOR IC CHIPS [patent_app_type] => utility [patent_app_number] => 16/056566 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 168521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056566
Logic drive based on standardized commodity programmable logic semiconductor IC chips Aug 6, 2018 Issued
Array ( [id] => 13936185 [patent_doc_number] => 20190051608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 16/057655 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057655 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057655
Semiconductor module Aug 6, 2018 Issued
Array ( [id] => 16308873 [patent_doc_number] => 10777684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Method of making a vertical pillar device and structure thereof [patent_app_type] => utility [patent_app_number] => 16/057612 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 6024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057612
Method of making a vertical pillar device and structure thereof Aug 6, 2018 Issued
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