
Thinh T. Nguyen
Examiner (ID: 17352, Phone: (571)272-1790 , Office: P/2897 )
| Most Active Art Unit | 2897 |
| Art Unit(s) | 2897, 2818 |
| Total Applications | 2487 |
| Issued Applications | 2130 |
| Pending Applications | 85 |
| Abandoned Applications | 277 |
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|---|---|---|---|
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