
Thinh T. Nguyen
Examiner (ID: 17352, Phone: (571)272-1790 , Office: P/2897 )
| Most Active Art Unit | 2897 |
| Art Unit(s) | 2897, 2818 |
| Total Applications | 2487 |
| Issued Applications | 2130 |
| Pending Applications | 85 |
| Abandoned Applications | 277 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11725293
[patent_doc_number] => 09698159
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-04
[patent_title] => 'Semiconductor structure with integrated passive structures'
[patent_app_type] => utility
[patent_app_number] => 14/864091
[patent_app_country] => US
[patent_app_date] => 2015-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 5077
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864091
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/864091 | Semiconductor structure with integrated passive structures | Sep 23, 2015 | Issued |
Array
(
[id] => 13862615
[patent_doc_number] => 10193035
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => Luminance pattern shaping using a back-emitting LED and a reflective substrate
[patent_app_type] => utility
[patent_app_number] => 15/510999
[patent_app_country] => US
[patent_app_date] => 2015-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 24
[patent_no_of_words] => 5494
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15510999
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/510999 | Luminance pattern shaping using a back-emitting LED and a reflective substrate | Sep 21, 2015 | Issued |
Array
(
[id] => 13862615
[patent_doc_number] => 10193035
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => Luminance pattern shaping using a back-emitting LED and a reflective substrate
[patent_app_type] => utility
[patent_app_number] => 15/510999
[patent_app_country] => US
[patent_app_date] => 2015-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 24
[patent_no_of_words] => 5494
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15510999
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/510999 | Luminance pattern shaping using a back-emitting LED and a reflective substrate | Sep 21, 2015 | Issued |
Array
(
[id] => 13862615
[patent_doc_number] => 10193035
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => Luminance pattern shaping using a back-emitting LED and a reflective substrate
[patent_app_type] => utility
[patent_app_number] => 15/510999
[patent_app_country] => US
[patent_app_date] => 2015-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 24
[patent_no_of_words] => 5494
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15510999
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/510999 | Luminance pattern shaping using a back-emitting LED and a reflective substrate | Sep 21, 2015 | Issued |
Array
(
[id] => 13862615
[patent_doc_number] => 10193035
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => Luminance pattern shaping using a back-emitting LED and a reflective substrate
[patent_app_type] => utility
[patent_app_number] => 15/510999
[patent_app_country] => US
[patent_app_date] => 2015-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 24
[patent_no_of_words] => 5494
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15510999
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/510999 | Luminance pattern shaping using a back-emitting LED and a reflective substrate | Sep 21, 2015 | Issued |
Array
(
[id] => 11510186
[patent_doc_number] => 09601352
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-21
[patent_title] => 'Method of localized annealing of semi-conducting elements using a reflective area'
[patent_app_type] => utility
[patent_app_number] => 14/859427
[patent_app_country] => US
[patent_app_date] => 2015-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 5454
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14859427
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/859427 | Method of localized annealing of semi-conducting elements using a reflective area | Sep 20, 2015 | Issued |
Array
(
[id] => 11660133
[patent_doc_number] => 09673145
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-06
[patent_title] => 'Semiconductor integrated circuit layout structure'
[patent_app_type] => utility
[patent_app_number] => 14/859367
[patent_app_country] => US
[patent_app_date] => 2015-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9343
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14859367
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/859367 | Semiconductor integrated circuit layout structure | Sep 20, 2015 | Issued |
Array
(
[id] => 10740947
[patent_doc_number] => 20160087098
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-24
[patent_title] => 'Semiconductor Devices Having Gate Structures and Methods of Manufacturing the Same'
[patent_app_type] => utility
[patent_app_number] => 14/859447
[patent_app_country] => US
[patent_app_date] => 2015-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 12675
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14859447
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/859447 | Semiconductor devices having gate structures and methods of manufacturing the same | Sep 20, 2015 | Issued |
Array
(
[id] => 11050796
[patent_doc_number] => 20160247754
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-25
[patent_title] => 'CONDUCTIVE POST PROTECTION FOR INTEGRATED CIRCUIT PACKAGES'
[patent_app_type] => utility
[patent_app_number] => 14/859318
[patent_app_country] => US
[patent_app_date] => 2015-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5561
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14859318
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/859318 | Conductive post protection for integrated circuit packages | Sep 19, 2015 | Issued |
Array
(
[id] => 11860358
[patent_doc_number] => 09740039
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-22
[patent_title] => 'Display device'
[patent_app_type] => utility
[patent_app_number] => 14/858061
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8845
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858061
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/858061 | Display device | Sep 17, 2015 | Issued |
Array
(
[id] => 11517470
[patent_doc_number] => 20170084544
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-23
[patent_title] => 'Integrated Circuit Dies Having Alignment Marks and Methods of Forming Same'
[patent_app_type] => utility
[patent_app_number] => 14/858923
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7003
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858923
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/858923 | Integrated circuit dies having alignment marks and methods of forming same | Sep 17, 2015 | Issued |
Array
(
[id] => 11111181
[patent_doc_number] => 20160308151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-20
[patent_title] => 'FLEXIBLE DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/859039
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3607
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14859039
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/859039 | Flexible display panel and method of manufacturing the same | Sep 17, 2015 | Issued |
Array
(
[id] => 11207982
[patent_doc_number] => 09437614
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-09-06
[patent_title] => 'Dual-semiconductor complementary metal-oxide-semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/858964
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 47
[patent_no_of_words] => 6917
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858964
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/858964 | Dual-semiconductor complementary metal-oxide-semiconductor device | Sep 17, 2015 | Issued |
Array
(
[id] => 11102427
[patent_doc_number] => 20160299397
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-13
[patent_title] => 'LIQUID CRYSTAL DISPLAY'
[patent_app_type] => utility
[patent_app_number] => 14/858020
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5864
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858020
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/858020 | Liquid crystal display | Sep 17, 2015 | Issued |
Array
(
[id] => 11539441
[patent_doc_number] => 09613856
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-04-04
[patent_title] => 'Method of forming metal interconnection'
[patent_app_type] => utility
[patent_app_number] => 14/858010
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 4439
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858010
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/858010 | Method of forming metal interconnection | Sep 17, 2015 | Issued |
Array
(
[id] => 11201300
[patent_doc_number] => 09431521
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-08-30
[patent_title] => 'Stress memorization technique for strain coupling enhancement in bulk finFET device'
[patent_app_type] => utility
[patent_app_number] => 14/858871
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 24
[patent_no_of_words] => 4598
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858871
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/858871 | Stress memorization technique for strain coupling enhancement in bulk finFET device | Sep 17, 2015 | Issued |
Array
(
[id] => 11517612
[patent_doc_number] => 20170084686
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-23
[patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/859153
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4964
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14859153
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/859153 | Semiconductor devices and methods of fabricating the same | Sep 17, 2015 | Issued |
Array
(
[id] => 12215007
[patent_doc_number] => 09911824
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-03-06
[patent_title] => 'Semiconductor structure with multi spacer'
[patent_app_type] => utility
[patent_app_number] => 14/858862
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 45
[patent_no_of_words] => 9870
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858862
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/858862 | Semiconductor structure with multi spacer | Sep 17, 2015 | Issued |
Array
(
[id] => 10645506
[patent_doc_number] => 09362383
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-06-07
[patent_title] => 'Highly scaled tunnel FET with tight pitch and method to fabricate same'
[patent_app_type] => utility
[patent_app_number] => 14/856811
[patent_app_country] => US
[patent_app_date] => 2015-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4209
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14856811
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/856811 | Highly scaled tunnel FET with tight pitch and method to fabricate same | Sep 16, 2015 | Issued |
Array
(
[id] => 10733250
[patent_doc_number] => 20160079399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-17
[patent_title] => 'Semiconductor Device And Manufacturing Method Thereof'
[patent_app_type] => utility
[patent_app_number] => 14/856621
[patent_app_country] => US
[patent_app_date] => 2015-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 14629
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14856621
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/856621 | Semiconductor device and manufacturing method thereof | Sep 16, 2015 | Issued |