
Tho Gia Phan
Examiner (ID: 17291, Phone: (571)272-1826 , Office: P/2845 )
| Most Active Art Unit | 2845 |
| Art Unit(s) | 2821, 2514, 2845, 2819, 3621 |
| Total Applications | 2846 |
| Issued Applications | 2484 |
| Pending Applications | 181 |
| Abandoned Applications | 216 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20141012
[patent_doc_number] => 20250248056
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-31
[patent_title] => METAL-INSULATOR-METAL CAPACITOR STRUCTURE AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/588016
[patent_app_country] => US
[patent_app_date] => 2024-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588016
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/588016 | METAL-INSULATOR-METAL CAPACITOR STRUCTURE AND FABRICATION METHOD THEREOF | Feb 26, 2024 | Pending |
Array
(
[id] => 20274878
[patent_doc_number] => 12444663
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Semiconductor package including a semiconductor die disposed in a cavity and method for manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 18/443338
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 1047
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443338
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/443338 | Semiconductor package including a semiconductor die disposed in a cavity and method for manufacturing thereof | Feb 15, 2024 | Issued |
Array
(
[id] => 20267125
[patent_doc_number] => 12438124
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-07
[patent_title] => Semiconductor package with routing patch and method of fabricating the semiconductor package
[patent_app_type] => utility
[patent_app_number] => 18/438638
[patent_app_country] => US
[patent_app_date] => 2024-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 0
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438638
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/438638 | Semiconductor package with routing patch and method of fabricating the semiconductor package | Feb 11, 2024 | Issued |
Array
(
[id] => 19648499
[patent_doc_number] => 20240423019
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/434871
[patent_app_country] => US
[patent_app_date] => 2024-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8412
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434871
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/434871 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE DISPLAY DEVICE | Feb 6, 2024 | Pending |
Array
(
[id] => 19775572
[patent_doc_number] => 20250056998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-13
[patent_title] => DISPLAY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/434822
[patent_app_country] => US
[patent_app_date] => 2024-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15095
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434822
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/434822 | DISPLAY APPARATUS | Feb 6, 2024 | Pending |
Array
(
[id] => 19191468
[patent_doc_number] => 20240170381
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => INTERCONNECT STRUCTURES AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/429708
[patent_app_country] => US
[patent_app_date] => 2024-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9110
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429708
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/429708 | INTERCONNECT STRUCTURES AND MANUFACTURING METHOD THEREOF | Jan 31, 2024 | Pending |
Array
(
[id] => 19351233
[patent_doc_number] => 20240260197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => WIRING SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/428062
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4063
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428062
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/428062 | WIRING SUBSTRATE | Jan 30, 2024 | Pending |
Array
(
[id] => 19606898
[patent_doc_number] => 20240397778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/427767
[patent_app_country] => US
[patent_app_date] => 2024-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22127
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427767
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/427767 | DISPLAY DEVICE | Jan 29, 2024 | Pending |
Array
(
[id] => 19972849
[patent_doc_number] => 12341474
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-24
[patent_title] => Transistor bias adjustment for optimization of third order intercept point in a cascode amplifier
[patent_app_type] => utility
[patent_app_number] => 18/427472
[patent_app_country] => US
[patent_app_date] => 2024-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3358
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427472
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/427472 | Transistor bias adjustment for optimization of third order intercept point in a cascode amplifier | Jan 29, 2024 | Issued |
Array
(
[id] => 19972499
[patent_doc_number] => 12341120
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-24
[patent_title] => Semiconductor chip and semiconductor device including a copper pillar and an intermediate layer
[patent_app_type] => utility
[patent_app_number] => 18/423463
[patent_app_country] => US
[patent_app_date] => 2024-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 35
[patent_no_of_words] => 6808
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423463
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/423463 | Semiconductor chip and semiconductor device including a copper pillar and an intermediate layer | Jan 25, 2024 | Issued |
Array
(
[id] => 19322163
[patent_doc_number] => 20240243710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => HIGH-BANDWIDTH LOAD-MODULATION POWER AMPLIFIER AND CORRESPONDING RADIO FREQUENCY FRONT-END MODULE
[patent_app_type] => utility
[patent_app_number] => 18/423243
[patent_app_country] => US
[patent_app_date] => 2024-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5826
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423243
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/423243 | HIGH-BANDWIDTH LOAD-MODULATION POWER AMPLIFIER AND CORRESPONDING RADIO FREQUENCY FRONT-END MODULE | Jan 24, 2024 | Pending |
Array
(
[id] => 19766072
[patent_doc_number] => 12224376
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-11
[patent_title] => Light-emitting display device and electronic device including a first pixel and a second pixel and an oxide semiconductor region overlapping a light-emitting region
[patent_app_type] => utility
[patent_app_number] => 18/417474
[patent_app_country] => US
[patent_app_date] => 2024-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 12985
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417474
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/417474 | Light-emitting display device and electronic device including a first pixel and a second pixel and an oxide semiconductor region overlapping a light-emitting region | Jan 18, 2024 | Issued |
Array
(
[id] => 19469090
[patent_doc_number] => 20240322760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => Constant VDS1 Bias Control for Stacked Transistor Configuration
[patent_app_type] => utility
[patent_app_number] => 18/406724
[patent_app_country] => US
[patent_app_date] => 2024-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 51544
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406724
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/406724 | Constant VDS1 Bias Control for Stacked Transistor Configuration | Jan 7, 2024 | Pending |
Array
(
[id] => 19130893
[patent_doc_number] => 20240136246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-25
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/403686
[patent_app_country] => US
[patent_app_date] => 2024-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14679
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403686
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/403686 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Jan 2, 2024 | Pending |
Array
(
[id] => 19823365
[patent_doc_number] => 20250081572
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/403692
[patent_app_country] => US
[patent_app_date] => 2024-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7662
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403692
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/403692 | SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME | Jan 2, 2024 | Pending |
Array
(
[id] => 19500958
[patent_doc_number] => 20240339976
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => RAIL-TO-RAIL INPUT STAGE CIRCUIT AND OPERATIONAL AMPLIFIER
[patent_app_type] => utility
[patent_app_number] => 18/401468
[patent_app_country] => US
[patent_app_date] => 2023-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4989
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401468
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/401468 | RAIL-TO-RAIL INPUT STAGE CIRCUIT AND OPERATIONAL AMPLIFIER | Dec 29, 2023 | Pending |
Array
(
[id] => 19943708
[patent_doc_number] => 12315845
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Electronic device having a substrate-to-substrate interconnection structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/400335
[patent_app_country] => US
[patent_app_date] => 2023-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4570
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400335
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/400335 | Electronic device having a substrate-to-substrate interconnection structure and manufacturing method thereof | Dec 28, 2023 | Issued |
Array
(
[id] => 19322153
[patent_doc_number] => 20240243700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => METHODS AND TECHNIQUES TO ACHIEVE TARGET PHASE SHIFT OVER WIDE FREQUENCY BAND IN THE INPUT OF DOHERTY POWER AMPLIFIERS
[patent_app_type] => utility
[patent_app_number] => 18/400451
[patent_app_country] => US
[patent_app_date] => 2023-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9700
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400451
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/400451 | METHODS AND TECHNIQUES TO ACHIEVE TARGET PHASE SHIFT OVER WIDE FREQUENCY BAND IN THE INPUT OF DOHERTY POWER AMPLIFIERS | Dec 28, 2023 | Pending |
Array
(
[id] => 19322162
[patent_doc_number] => 20240243709
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => METHODS AND TECHNIQUES TO IMPROVE STABILITY OF CASCODE AMPLIFIERS AND ENHANCE LINEUP EFFICIENCY IN MULTI-STAGE POWER AMPLIFIERS
[patent_app_type] => utility
[patent_app_number] => 18/400433
[patent_app_country] => US
[patent_app_date] => 2023-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6004
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400433
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/400433 | METHODS AND TECHNIQUES TO IMPROVE STABILITY OF CASCODE AMPLIFIERS AND ENHANCE LINEUP EFFICIENCY IN MULTI-STAGE POWER AMPLIFIERS | Dec 28, 2023 | Pending |
Array
(
[id] => 19270234
[patent_doc_number] => 20240213940
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => ELECTRIC CIRCUIT PROVIDING MIXING AND GAINING FUNCTIONS FOR A RF RECEIVER FRONT-END AND RF RECEIVER FRONT-END
[patent_app_type] => utility
[patent_app_number] => 18/543264
[patent_app_country] => US
[patent_app_date] => 2023-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8844
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543264
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/543264 | ELECTRIC CIRCUIT PROVIDING MIXING AND GAINING FUNCTIONS FOR A RF RECEIVER FRONT-END AND RF RECEIVER FRONT-END | Dec 17, 2023 | Pending |