Thomas A. Waltz

Array ( [id] => 19445162 [patent_doc_number] => 12095459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Anti-aging clock source multiplexing [patent_app_type] => utility [patent_app_number] => 17/805014 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 12 [patent_no_of_words] => 13220 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19094502 [patent_doc_number] => 11955973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-09 [patent_title] => System and method for skyrmion based logic device [patent_app_type] => utility [patent_app_number] => 17/829109 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4035 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17871714 [patent_doc_number] => 20220294451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => METHOD AND APPARATUS FOR PROVIDING FIELD-PROGRAMMABLE GATE ARRAY (FPGA) INTEGRATED CIRCUIT (IC) PACKAGE [patent_app_type] => utility [patent_app_number] => 17/828037 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18913520 [patent_doc_number] => 11876515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Transceiver and method of driving the same [patent_app_type] => utility [patent_app_number] => 17/825622 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19487597 [patent_doc_number] => 12107326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Compact antenna system for munition [patent_app_type] => utility [patent_app_number] => 17/825389 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 11082 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18041072 [patent_doc_number] => 20220385289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => INTEGRATED CIRCUIT, CIRCUIT BOARD, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/748798 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18705302 [patent_doc_number] => 11791824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-17 [patent_title] => Voltage domain GPIO control [patent_app_type] => utility [patent_app_number] => 17/741477 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10269 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17811675 [patent_doc_number] => 20220263510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => STACKED INTEGRATED PLATFORM ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/734297 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19733640 [patent_doc_number] => 12211641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-28 [patent_title] => System and method for skyrmion based logic device [patent_app_type] => utility [patent_app_number] => 17/734061 [patent_app_country] => US [patent_app_date] => 2022-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18744166 [patent_doc_number] => 20230353154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => INPUT SIGNAL SHAPING FOR A PROGRAMMABLE LOGIC ARRAY [patent_app_type] => utility [patent_app_number] => 17/733934 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19611350 [patent_doc_number] => 12160236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Reference voltage circuit with temperature compensation [patent_app_type] => utility [patent_app_number] => 17/661093 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 37 [patent_no_of_words] => 11445 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17899711 [patent_doc_number] => 20220309373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => METHODS AND SYSTEMS OF FULLY-RANDOMIZED BENCHMARKING FOR QUANTUM CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/660744 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17766746 [patent_doc_number] => 20220240360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => LOAD CONTROL DEVICE FOR CONTROLLING A DRIVER FOR A LIGHTING LOAD [patent_app_type] => utility [patent_app_number] => 17/717670 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17753484 [patent_doc_number] => 20220231689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => STACKED PROGRAMMABLE INTEGRATED CIRCUITRY WITH SMART MEMORY [patent_app_type] => utility [patent_app_number] => 17/713030 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18680942 [patent_doc_number] => 20230318605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => CUSTOMIZING A SEMICONDUCTOR PRODUCT [patent_app_type] => utility [patent_app_number] => 17/711851 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18440842 [patent_doc_number] => 20230188138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => METHODS AND APPARATUS TO BALANCE PROPAGATION DELAY AND BUS EMISSIONS IN TRANSCEIVERS [patent_app_type] => utility [patent_app_number] => 17/709734 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17738876 [patent_doc_number] => 20220224338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => PROGRAMMABLE DEVICE HAVING HARDENED CIRCUITS FOR PREDETERMINED DIGITAL SIGNAL PROCESSING FUNCTIONALITY [patent_app_type] => utility [patent_app_number] => 17/709167 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18156819 [patent_doc_number] => 11569820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Programmable device having hardened circuits for predetermined digital signal processing functionality [patent_app_type] => utility [patent_app_number] => 17/709164 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5707 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18464903 [patent_doc_number] => 11689203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-27 [patent_title] => Method and apparatus for symmetric aging of clock trees [patent_app_type] => utility [patent_app_number] => 17/655697 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 9692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18999688 [patent_doc_number] => 11916551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA [patent_app_type] => utility [patent_app_number] => 17/676123 [patent_app_country] => US [patent_app_date] => 2022-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 15622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676123 [rel_patent_id] =>[rel_patent_doc_number] =>)