| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2765387
[patent_doc_number] => 05043875
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-27
[patent_title] => 'Communication system with information being exchanged among different partitions of a switching function and simultaneously blocking some partitions from receiving external stimuli'
[patent_app_type] => 1
[patent_app_number] => 7/290876
[patent_app_country] => US
[patent_app_date] => 1988-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3149
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/043/05043875.pdf
[firstpage_image] =>[orig_patent_app_number] => 290876
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/290876 | Communication system with information being exchanged among different partitions of a switching function and simultaneously blocking some partitions from receiving external stimuli | Dec 27, 1988 | Issued |
| 07/288540 | SYSTEM FOR MANAGEMENT OF THE PRIORITIES OF ACCESS TO A MEMORY AND ITS APPLICATION | Dec 20, 1988 | Abandoned |
Array
(
[id] => 2646297
[patent_doc_number] => 04914574
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-03
[patent_title] => 'Data transmission apparatus having cascaded data processing modules for daisy chain data transfer'
[patent_app_type] => 1
[patent_app_number] => 7/286874
[patent_app_country] => US
[patent_app_date] => 1988-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 28
[patent_no_of_words] => 10122
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/914/04914574.pdf
[firstpage_image] =>[orig_patent_app_number] => 286874
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/286874 | Data transmission apparatus having cascaded data processing modules for daisy chain data transfer | Dec 19, 1988 | Issued |
Array
(
[id] => 2654762
[patent_doc_number] => 04980819
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-12-25
[patent_title] => 'Mechanism for automatically updating multiple unit register file memories in successive cycles for a pipelined processing system'
[patent_app_type] => 1
[patent_app_number] => 7/286551
[patent_app_country] => US
[patent_app_date] => 1988-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 7
[patent_no_of_words] => 6129
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/980/04980819.pdf
[firstpage_image] =>[orig_patent_app_number] => 286551
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/286551 | Mechanism for automatically updating multiple unit register file memories in successive cycles for a pipelined processing system | Dec 18, 1988 | Issued |
| 07/285187 | DATA PROCESSOR SYSTEM | Dec 14, 1988 | Abandoned |
Array
(
[id] => 2594169
[patent_doc_number] => 04963909
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-16
[patent_title] => 'Camera system for selectively generating new memory address when a new switching state is different from a previous switching state'
[patent_app_type] => 1
[patent_app_number] => 7/284907
[patent_app_country] => US
[patent_app_date] => 1988-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3386
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/963/04963909.pdf
[firstpage_image] =>[orig_patent_app_number] => 284907
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/284907 | Camera system for selectively generating new memory address when a new switching state is different from a previous switching state | Dec 14, 1988 | Issued |
| 07/282629 | HIGH-PERFORMANCE FAULTTOLERANT COMPUTER SYSTEM HAVING THREE PROCESSORS AND TWO MEMORY MUDULES | Dec 8, 1988 | Abandoned |
| 07/282538 | SYNCHRONIZATION OF INTERRUPTS BY CYCLE COUNT IN FAULT-TOLERANT COMPUTER SYSTEM | Dec 8, 1988 | Abandoned |
| 07/281261 | COMPUTER BUS INTERCONNECTION DEVICE | Dec 6, 1988 | Abandoned |
Array
(
[id] => 2707416
[patent_doc_number] => 04989130
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-29
[patent_title] => 'System for determining and storing valid status information received from cross coupled unit'
[patent_app_type] => 1
[patent_app_number] => 7/280884
[patent_app_country] => US
[patent_app_date] => 1988-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 8962
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 291
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/989/04989130.pdf
[firstpage_image] =>[orig_patent_app_number] => 280884
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/280884 | System for determining and storing valid status information received from cross coupled unit | Dec 6, 1988 | Issued |
Array
(
[id] => 2754330
[patent_doc_number] => 05003471
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-26
[patent_title] => 'Windowed programmable data transferring apparatus which uses a selective number of address offset registers and synchronizes memory access to buffer'
[patent_app_type] => 1
[patent_app_number] => 7/277415
[patent_app_country] => US
[patent_app_date] => 1988-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7510
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/003/05003471.pdf
[firstpage_image] =>[orig_patent_app_number] => 277415
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/277415 | Windowed programmable data transferring apparatus which uses a selective number of address offset registers and synchronizes memory access to buffer | Nov 28, 1988 | Issued |
| 07/277385 | METHOD OF FILING STAPLED DOCUMENTS WITHIN A CONTEXT OF A FOLDER | Nov 28, 1988 | Abandoned |
Array
(
[id] => 2707473
[patent_doc_number] => 04989133
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-29
[patent_title] => 'System for executing, scheduling, and selectively linking time dependent processes based upon scheduling time thereof'
[patent_app_type] => 1
[patent_app_number] => 7/274741
[patent_app_country] => US
[patent_app_date] => 1988-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 40
[patent_no_of_words] => 18604
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/989/04989133.pdf
[firstpage_image] =>[orig_patent_app_number] => 274741
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/274741 | System for executing, scheduling, and selectively linking time dependent processes based upon scheduling time thereof | Nov 13, 1988 | Issued |
| 07/269645 | DATA PROCESSOR FOR PROVIDING INSTRUCTIONS TO RESOURCES WITHOUT INTERVAL | Nov 9, 1988 | Abandoned |
Array
(
[id] => 2632627
[patent_doc_number] => 04956772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-11
[patent_title] => 'Methods of selecting simultaneously transmitted messages in a multiprocessor system'
[patent_app_type] => 1
[patent_app_number] => 7/266899
[patent_app_country] => US
[patent_app_date] => 1988-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 39
[patent_no_of_words] => 28374
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/956/04956772.pdf
[firstpage_image] =>[orig_patent_app_number] => 266899
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/266899 | Methods of selecting simultaneously transmitted messages in a multiprocessor system | Nov 2, 1988 | Issued |
| 07/266271 | MANAGING OBJECT RELATIONSHIPS | Oct 25, 1988 | Abandoned |
| 07/263429 | COMPUTER ANIMATION PRODUCTION SYSTEM | Oct 23, 1988 | Abandoned |
| 07/260783 | MULTIPROCESSOR SYSTEM UTILIZING PROCESSOR GROUP IDENTIFIERS | Oct 20, 1988 | Abandoned |
Array
(
[id] => 2697195
[patent_doc_number] => 05050066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-17
[patent_title] => 'Apparatus with a single memory and a plurality of queue counters for queuing requests and replies on a pipelined packet bus'
[patent_app_type] => 1
[patent_app_number] => 7/257857
[patent_app_country] => US
[patent_app_date] => 1988-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 8304
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/050/05050066.pdf
[firstpage_image] =>[orig_patent_app_number] => 257857
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/257857 | Apparatus with a single memory and a plurality of queue counters for queuing requests and replies on a pipelined packet bus | Oct 13, 1988 | Issued |
Array
(
[id] => 2671464
[patent_doc_number] => 04947317
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-08-07
[patent_title] => 'Communication protocol for a three nodes system having dedicated connections and bit indicating function of exchanged message'
[patent_app_type] => 1
[patent_app_number] => 7/256811
[patent_app_country] => US
[patent_app_date] => 1988-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 38
[patent_no_of_words] => 9103
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 471
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/947/04947317.pdf
[firstpage_image] =>[orig_patent_app_number] => 256811
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/256811 | Communication protocol for a three nodes system having dedicated connections and bit indicating function of exchanged message | Oct 11, 1988 | Issued |