| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2606023
[patent_doc_number] => 04924378
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-08
[patent_title] => 'License mangagement system and license storage key'
[patent_app_type] => 1
[patent_app_number] => 7/205986
[patent_app_country] => US
[patent_app_date] => 1988-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7475
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/924/04924378.pdf
[firstpage_image] =>[orig_patent_app_number] => 205986
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/205986 | License mangagement system and license storage key | Jun 12, 1988 | Issued |
Array
(
[id] => 2639591
[patent_doc_number] => 04958274
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-18
[patent_title] => 'System with a N stages timing silo and P stages information silo for soloing information'
[patent_app_type] => 1
[patent_app_number] => 7/201481
[patent_app_country] => US
[patent_app_date] => 1988-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4001
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/958/04958274.pdf
[firstpage_image] =>[orig_patent_app_number] => 201481
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/201481 | System with a N stages timing silo and P stages information silo for soloing information | May 31, 1988 | Issued |
| 07/205043 | COMPUTER SYSTEM HAVING DELAYED SAVE ON PROCEDURE CALLS | May 30, 1988 | Abandoned |
Array
(
[id] => 2601374
[patent_doc_number] => 04941084
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-07-10
[patent_title] => 'System for locating resources resided in a distributing processing system by sequentially transmitting resource inquiries through a looped transmission line'
[patent_app_type] => 1
[patent_app_number] => 7/201290
[patent_app_country] => US
[patent_app_date] => 1988-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2165
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/941/04941084.pdf
[firstpage_image] =>[orig_patent_app_number] => 201290
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/201290 | System for locating resources resided in a distributing processing system by sequentially transmitting resource inquiries through a looped transmission line | May 26, 1988 | Issued |
Array
(
[id] => 2487092
[patent_doc_number] => 04882702
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-11-21
[patent_title] => 'Programmable controller with I/O expansion module located in one of I/O module positions for communication with outside I/O modules'
[patent_app_type] => 1
[patent_app_number] => 7/195407
[patent_app_country] => US
[patent_app_date] => 1988-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 12938
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/882/04882702.pdf
[firstpage_image] =>[orig_patent_app_number] => 195407
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/195407 | Programmable controller with I/O expansion module located in one of I/O module positions for communication with outside I/O modules | May 15, 1988 | Issued |
Array
(
[id] => 2753430
[patent_doc_number] => 04987536
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-22
[patent_title] => 'Communication system for sending an identical routing tree to all connected nodes to establish a shortest route and transmitting messages thereafter'
[patent_app_type] => 1
[patent_app_number] => 7/193391
[patent_app_country] => US
[patent_app_date] => 1988-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3241
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/987/04987536.pdf
[firstpage_image] =>[orig_patent_app_number] => 193391
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/193391 | Communication system for sending an identical routing tree to all connected nodes to establish a shortest route and transmitting messages thereafter | May 11, 1988 | Issued |
Array
(
[id] => 2607070
[patent_doc_number] => 04924434
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-08
[patent_title] => 'Sharing word-processing functions among multiple processors'
[patent_app_type] => 1
[patent_app_number] => 7/196833
[patent_app_country] => US
[patent_app_date] => 1988-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4436
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 333
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/924/04924434.pdf
[firstpage_image] =>[orig_patent_app_number] => 196833
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/196833 | Sharing word-processing functions among multiple processors | May 8, 1988 | Issued |
Array
(
[id] => 2754871
[patent_doc_number] => 05012406
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-30
[patent_title] => 'Line of power interruption in predetermined area of internal permanent memory'
[patent_app_type] => 1
[patent_app_number] => 7/183674
[patent_app_country] => US
[patent_app_date] => 1988-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 7451
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/012/05012406.pdf
[firstpage_image] =>[orig_patent_app_number] => 183674
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/183674 | Line of power interruption in predetermined area of internal permanent memory | Apr 18, 1988 | Issued |
Array
(
[id] => 2752425
[patent_doc_number] => 05029080
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-02
[patent_title] => 'Method and apparatus for composing a set of instructions for executing a data flow program defined by structured data'
[patent_app_type] => 1
[patent_app_number] => 7/181586
[patent_app_country] => US
[patent_app_date] => 1988-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 33
[patent_no_of_words] => 4621
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/029/05029080.pdf
[firstpage_image] =>[orig_patent_app_number] => 181586
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/181586 | Method and apparatus for composing a set of instructions for executing a data flow program defined by structured data | Apr 13, 1988 | Issued |
Array
(
[id] => 2594329
[patent_doc_number] => 04926317
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-15
[patent_title] => 'Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of physical addresses'
[patent_app_type] => 1
[patent_app_number] => 7/183355
[patent_app_country] => US
[patent_app_date] => 1988-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 11484
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/926/04926317.pdf
[firstpage_image] =>[orig_patent_app_number] => 183355
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/183355 | Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of physical addresses | Apr 11, 1988 | Issued |
Array
(
[id] => 2663981
[patent_doc_number] => 04962449
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-09
[patent_title] => 'Computer security system having remote location recognition and remote location lock-out'
[patent_app_type] => 1
[patent_app_number] => 7/180089
[patent_app_country] => US
[patent_app_date] => 1988-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 7131
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 343
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/962/04962449.pdf
[firstpage_image] =>[orig_patent_app_number] => 180089
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/180089 | Computer security system having remote location recognition and remote location lock-out | Apr 10, 1988 | Issued |
Array
(
[id] => 2571509
[patent_doc_number] => 04945474
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-07-31
[patent_title] => 'Method for restoring a database after I/O error employing write-ahead logging protocols'
[patent_app_type] => 1
[patent_app_number] => 7/179195
[patent_app_country] => US
[patent_app_date] => 1988-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 7035
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/945/04945474.pdf
[firstpage_image] =>[orig_patent_app_number] => 179195
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/179195 | Method for restoring a database after I/O error employing write-ahead logging protocols | Apr 7, 1988 | Issued |
| 07/178291 | TOPOGRAPHY FOR SIXTEEN BIT CMOS MICROPROCESSOR WITH EIGHT BIT EMULATION AND ABORT CAPABILITY | Apr 5, 1988 | Abandoned |
Array
(
[id] => 2486128
[patent_doc_number] => 04876639
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-24
[patent_title] => 'Method and circuitry for causing sixteen bit microprocessor to execute eight bit op codes to produce either internal sixteen bit operation or internal eight bit operation in accordance with an emulation bit'
[patent_app_type] => 1
[patent_app_number] => 7/178429
[patent_app_country] => US
[patent_app_date] => 1988-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 24
[patent_no_of_words] => 14968
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/876/04876639.pdf
[firstpage_image] =>[orig_patent_app_number] => 178429
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/178429 | Method and circuitry for causing sixteen bit microprocessor to execute eight bit op codes to produce either internal sixteen bit operation or internal eight bit operation in accordance with an emulation bit | Apr 5, 1988 | Issued |
Array
(
[id] => 2530336
[patent_doc_number] => 04881165
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-11-14
[patent_title] => 'Method and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systems'
[patent_app_type] => 1
[patent_app_number] => 7/176474
[patent_app_country] => US
[patent_app_date] => 1988-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4980
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 259
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/881/04881165.pdf
[firstpage_image] =>[orig_patent_app_number] => 176474
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/176474 | Method and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systems | Mar 31, 1988 | Issued |
| 07/173501 | MULTIPLE ADDRESS-SPACE DATA PROCESSOR WITH ADDRESSABLE REGISTER AND CONTEXT SWITCHING | Mar 23, 1988 | Abandoned |
| 07/170924 | RETAIL VIDEO RECORDING BOOTH | Mar 20, 1988 | Abandoned |
Array
(
[id] => 2611873
[patent_doc_number] => 04912628
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-27
[patent_title] => 'Suspending and resuming processing of tasks running in a virtual machine data processing system'
[patent_app_type] => 1
[patent_app_number] => 7/168300
[patent_app_country] => US
[patent_app_date] => 1988-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5654
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/912/04912628.pdf
[firstpage_image] =>[orig_patent_app_number] => 168300
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/168300 | Suspending and resuming processing of tasks running in a virtual machine data processing system | Mar 14, 1988 | Issued |
Array
(
[id] => 2664472
[patent_doc_number] => 04962475
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-09
[patent_title] => 'Method for generating a document utilizing a plurality of windows associated with different data objects'
[patent_app_type] => 1
[patent_app_number] => 7/168368
[patent_app_country] => US
[patent_app_date] => 1988-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4001
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/962/04962475.pdf
[firstpage_image] =>[orig_patent_app_number] => 168368
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/168368 | Method for generating a document utilizing a plurality of windows associated with different data objects | Mar 14, 1988 | Issued |
Array
(
[id] => 2641030
[patent_doc_number] => 04937740
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-26
[patent_title] => 'Real time software analyzing system for storing selective m-bit addresses based upon correspondingly generated n-bit tags'
[patent_app_type] => 1
[patent_app_number] => 7/161284
[patent_app_country] => US
[patent_app_date] => 1988-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2922
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/937/04937740.pdf
[firstpage_image] =>[orig_patent_app_number] => 161284
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/161284 | Real time software analyzing system for storing selective m-bit addresses based upon correspondingly generated n-bit tags | Feb 28, 1988 | Issued |