Search

Thomas C. Lee

Supervisory Patent Examiner (ID: 8042, Phone: (571)272-3667 , Office: P/2115 )

Most Active Art Unit
2302
Art Unit(s)
2182, 2302, 2307, 2115, 2317, 2782, 2185
Total Applications
699
Issued Applications
429
Pending Applications
25
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
07/094306 SESSION CONTROL IN NETWORK FOR DIGITAL DATA PROCESSING SYSTEM WHICH SUPPORTS MULTIPLE TRANSFER PROTOCOLS Sep 3, 1987 Abandoned
Array ( [id] => 2702061 [patent_doc_number] => 05019966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-28 [patent_title] => 'Dual processors using busy signal for controlling transfer for predetermined length data when receiving processor is processing previously received data' [patent_app_type] => 1 [patent_app_number] => 7/091813 [patent_app_country] => US [patent_app_date] => 1987-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8798 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/019/05019966.pdf [firstpage_image] =>[orig_patent_app_number] => 091813 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/091813
Dual processors using busy signal for controlling transfer for predetermined length data when receiving processor is processing previously received data Aug 31, 1987 Issued
07/088622 DATA INTEGRATION BY OBJECT MANAGEMENT Aug 20, 1987 Abandoned
Array ( [id] => 2485192 [patent_doc_number] => 04812972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-14 [patent_title] => 'Microcode computer having dispatch and main control stores for storing the first and the remaining microinstructions of machine instructions' [patent_app_type] => 1 [patent_app_number] => 7/088470 [patent_app_country] => US [patent_app_date] => 1987-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 11579 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/812/04812972.pdf [firstpage_image] =>[orig_patent_app_number] => 088470 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/088470
Microcode computer having dispatch and main control stores for storing the first and the remaining microinstructions of machine instructions Aug 18, 1987 Issued
Array ( [id] => 2391128 [patent_doc_number] => 04789962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-06 [patent_title] => 'Methods of displaying help information nearest to an operation point at which the help information is requested' [patent_app_type] => 1 [patent_app_number] => 7/080180 [patent_app_country] => US [patent_app_date] => 1987-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3193 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/789/04789962.pdf [firstpage_image] =>[orig_patent_app_number] => 080180 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/080180
Methods of displaying help information nearest to an operation point at which the help information is requested Jul 29, 1987 Issued
Array ( [id] => 2451819 [patent_doc_number] => 04757445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-07-12 [patent_title] => 'Method and apparatus for validating prefetched instruction' [patent_app_type] => 1 [patent_app_number] => 7/079191 [patent_app_country] => US [patent_app_date] => 1987-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4998 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/757/04757445.pdf [firstpage_image] =>[orig_patent_app_number] => 079191 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/079191
Method and apparatus for validating prefetched instruction Jul 28, 1987 Issued
07/078886 FLEXIBLE CHANNEL CONTROL SYSTEM FOR USE WITH INTELLIGENT I/O CONTROLLER Jul 28, 1987 Abandoned
Array ( [id] => 2527328 [patent_doc_number] => 04864495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-05 [patent_title] => 'Apparatus for controlling vacant areas in buffer memory in a pocket transmission system' [patent_app_type] => 1 [patent_app_number] => 7/079163 [patent_app_country] => US [patent_app_date] => 1987-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2933 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/864/04864495.pdf [firstpage_image] =>[orig_patent_app_number] => 079163 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/079163
Apparatus for controlling vacant areas in buffer memory in a pocket transmission system Jul 28, 1987 Issued
07/078022 HIERARCHICAL ADDRESS CACHE SYSTEM FOR COMPUTER Jul 23, 1987 Abandoned
07/075258 METHOD FOR SPEEDING MEMORY ACCESS REQUESTS AND A CIRCUIT FOR CARRYING OUT THE SAME Jul 15, 1987 Abandoned
07/073717 A HIGH-SPEED MULTIPROCESSOR SYSTEM HAVING READUCED NETWORK TRAFFIC Jul 14, 1987 Abandoned
Array ( [id] => 2606902 [patent_doc_number] => 04924425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-08 [patent_title] => 'Method for immediately writing an operand to a selected word location within a block of a buffer memory' [patent_app_type] => 1 [patent_app_number] => 7/073281 [patent_app_country] => US [patent_app_date] => 1987-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 4285 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/924/04924425.pdf [firstpage_image] =>[orig_patent_app_number] => 073281 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/073281
Method for immediately writing an operand to a selected word location within a block of a buffer memory Jul 7, 1987 Issued
Array ( [id] => 2450686 [patent_doc_number] => 04779193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-18 [patent_title] => 'Data processing apparatus for writing calculation result into buffer memory after the writing of the beginning word of the read data' [patent_app_type] => 1 [patent_app_number] => 7/073372 [patent_app_country] => US [patent_app_date] => 1987-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4250 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/779/04779193.pdf [firstpage_image] =>[orig_patent_app_number] => 073372 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/073372
Data processing apparatus for writing calculation result into buffer memory after the writing of the beginning word of the read data Jul 7, 1987 Issued
Array ( [id] => 2596477 [patent_doc_number] => 04928238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-22 [patent_title] => 'Scalar data arithmetic control system for vector arithmetic processor' [patent_app_type] => 1 [patent_app_number] => 7/069102 [patent_app_country] => US [patent_app_date] => 1987-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2217 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/928/04928238.pdf [firstpage_image] =>[orig_patent_app_number] => 069102 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/069102
Scalar data arithmetic control system for vector arithmetic processor Jul 1, 1987 Issued
Array ( [id] => 3450322 [patent_doc_number] => 05420464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'RF voltage/current sensor apparatus' [patent_app_type] => 1 [patent_app_number] => 7/068739 [patent_app_country] => US [patent_app_date] => 1992-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1875 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420464.pdf [firstpage_image] =>[orig_patent_app_number] => 068739 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/068739
Method for maintaining data integrity during information transmission by generating indicia representing total number of binary 1's and 0's of the data Jun 29, 1987 Issued
Array ( [id] => 3450322 [patent_doc_number] => 05420464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'RF voltage/current sensor apparatus' [patent_app_type] => 1 [patent_app_number] => 7/068739 [patent_app_country] => US [patent_app_date] => 1992-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1875 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420464.pdf [firstpage_image] =>[orig_patent_app_number] => 068739 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/068739
Method for maintaining data integrity during information transmission by generating indicia representing total number of binary 1's and 0's of the data Jun 29, 1987 Issued
Array ( [id] => 2532339 [patent_doc_number] => 04884234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-28 [patent_title] => 'Dynamic RAM refresh circuit with DMA access' [patent_app_type] => 1 [patent_app_number] => 7/067761 [patent_app_country] => US [patent_app_date] => 1987-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 14622 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/884/04884234.pdf [firstpage_image] =>[orig_patent_app_number] => 067761 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/067761
Dynamic RAM refresh circuit with DMA access Jun 28, 1987 Issued
Array ( [id] => 2486205 [patent_doc_number] => 04876643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-24 [patent_title] => 'Parallel searching system having a master processor for controlling plural slave processors for independently processing respective search requests' [patent_app_type] => 1 [patent_app_number] => 7/066129 [patent_app_country] => US [patent_app_date] => 1987-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5006 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/876/04876643.pdf [firstpage_image] =>[orig_patent_app_number] => 066129 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/066129
Parallel searching system having a master processor for controlling plural slave processors for independently processing respective search requests Jun 23, 1987 Issued
07/065372 BLOCK DIAGRAM SIMULATOR WITH CONTROL CAPABILITY Jun 21, 1987 Abandoned
Array ( [id] => 2393304 [patent_doc_number] => 04724518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-02-09 [patent_title] => 'Odd/even storage in cache memory' [patent_app_type] => 1 [patent_app_number] => 7/065160 [patent_app_country] => US [patent_app_date] => 1987-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2181 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/724/04724518.pdf [firstpage_image] =>[orig_patent_app_number] => 065160 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/065160
Odd/even storage in cache memory Jun 15, 1987 Issued
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