Search

Thomas C. Lee

Supervisory Patent Examiner (ID: 864, Phone: (571)272-3667 , Office: P/2115 )

Most Active Art Unit
2302
Art Unit(s)
2317, 2182, 2302, 2185, 2782, 2115, 2307
Total Applications
703
Issued Applications
429
Pending Applications
30
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
07/019916 ENHJANCED BLOCK PAGING EMPLOYING GLOBAL LEAST RECENTLY USED MEMORY MANAGEMENT Feb 24, 1987 Abandoned
Array ( [id] => 2563227 [patent_doc_number] => 04897781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-30 [patent_title] => 'System and method for using cached data at a local node after re-opening a file at a remote node in a distributed networking environment' [patent_app_type] => 1 [patent_app_number] => 7/014899 [patent_app_country] => US [patent_app_date] => 1987-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9519 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/897/04897781.pdf [firstpage_image] =>[orig_patent_app_number] => 014899 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/014899
System and method for using cached data at a local node after re-opening a file at a remote node in a distributed networking environment Feb 12, 1987 Issued
07/014760 DATA PROCESSING SYSTEM WITH EXTERNAL DEVICE CONTROLLER Feb 12, 1987 Abandoned
Array ( [id] => 2523304 [patent_doc_number] => 04851990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-25 [patent_title] => 'High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure' [patent_app_type] => 1 [patent_app_number] => 7/012226 [patent_app_country] => US [patent_app_date] => 1987-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 9871 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/851/04851990.pdf [firstpage_image] =>[orig_patent_app_number] => 012226 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/012226
High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure Feb 8, 1987 Issued
Array ( [id] => 2601437 [patent_doc_number] => 04918594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-17 [patent_title] => 'Method and system for logical simulation of information processing system including logic circuit model and logic function model' [patent_app_type] => 1 [patent_app_number] => 7/011068 [patent_app_country] => US [patent_app_date] => 1987-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6132 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/918/04918594.pdf [firstpage_image] =>[orig_patent_app_number] => 011068 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/011068
Method and system for logical simulation of information processing system including logic circuit model and logic function model Feb 3, 1987 Issued
Array ( [id] => 2423907 [patent_doc_number] => 04747074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-24 [patent_title] => 'Display controller for detecting predetermined drawing command among a plurality of drawing commands' [patent_app_type] => 1 [patent_app_number] => 7/006963 [patent_app_country] => US [patent_app_date] => 1987-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2817 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/747/04747074.pdf [firstpage_image] =>[orig_patent_app_number] => 006963 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/006963
Display controller for detecting predetermined drawing command among a plurality of drawing commands Jan 26, 1987 Issued
Array ( [id] => 2571512 [patent_doc_number] => 04835677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-30 [patent_title] => 'System for directly and indirectly accessing control registers by different operating systems based upon value of operating system indication bit' [patent_app_type] => 1 [patent_app_number] => 7/008155 [patent_app_country] => US [patent_app_date] => 1987-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1394 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/835/04835677.pdf [firstpage_image] =>[orig_patent_app_number] => 008155 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/008155
System for directly and indirectly accessing control registers by different operating systems based upon value of operating system indication bit Jan 20, 1987 Issued
Array ( [id] => 2651398 [patent_doc_number] => 04939644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-03 [patent_title] => 'Input/output controller for controlling the sequencing of the execution of input/output commands in a data processing system' [patent_app_type] => 1 [patent_app_number] => 7/004757 [patent_app_country] => US [patent_app_date] => 1987-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8773 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/939/04939644.pdf [firstpage_image] =>[orig_patent_app_number] => 004757 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/004757
Input/output controller for controlling the sequencing of the execution of input/output commands in a data processing system Jan 8, 1987 Issued
Array ( [id] => 2577944 [patent_doc_number] => 04901232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-13 [patent_title] => 'I/O controller for controlling the sequencing of execution of I/O commands and for permitting modification of I/O controller operation by a host processor' [patent_app_type] => 1 [patent_app_number] => 7/005353 [patent_app_country] => US [patent_app_date] => 1987-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8687 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/901/04901232.pdf [firstpage_image] =>[orig_patent_app_number] => 005353 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/005353
I/O controller for controlling the sequencing of execution of I/O commands and for permitting modification of I/O controller operation by a host processor Jan 8, 1987 Issued
06/947642 MICROPROGRAM CONTROL APPARATUS USING DON'T CARE BITS AS PART OF ADDRESS BITS FOR COMMON INSTRUCTION AND GENERATING VARIABLE CONTROL BITS Dec 29, 1986 Issued
06/941704 HANDLING OF INTER-PROCESS NOTIFICATION OF ASYNCHRONOUS EVENTS IN A MULTIPROCESSOR SYSTEM Dec 21, 1986 Abandoned
06/942095 METHOD AND APPARATUS FOR VIDEOTEX INFORMATION RETRIEVAL Dec 14, 1986 Abandoned
Array ( [id] => 2523756 [patent_doc_number] => 04819154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-04 [patent_title] => 'Memory back up system with one cache memory and two physically separated main memories' [patent_app_type] => 1 [patent_app_number] => 6/937978 [patent_app_country] => US [patent_app_date] => 1986-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 9 [patent_no_of_words] => 22374 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/819/04819154.pdf [firstpage_image] =>[orig_patent_app_number] => 937978 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/937978
Memory back up system with one cache memory and two physically separated main memories Dec 3, 1986 Issued
Array ( [id] => 2749515 [patent_doc_number] => RE033521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-15 [patent_title] => 'Method and apparatus for detecting a faulty computer in a multicomputer system' [patent_app_type] => 2 [patent_app_number] => 6/938034 [patent_app_country] => US [patent_app_date] => 1986-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4712 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/033/RE033521.pdf [firstpage_image] =>[orig_patent_app_number] => 938034 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/938034
Method and apparatus for detecting a faulty computer in a multicomputer system Dec 3, 1986 Issued
06/937355 INSTRUMENT CONTROL SYSTEM AND METHOD Dec 2, 1986 Abandoned
Array ( [id] => 2490247 [patent_doc_number] => 04823261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-18 [patent_title] => 'Multiprocessor system for updating status information through flip-flopping read version and write version of checkpoint data' [patent_app_type] => 1 [patent_app_number] => 6/934378 [patent_app_country] => US [patent_app_date] => 1986-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 16158 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/823/04823261.pdf [firstpage_image] =>[orig_patent_app_number] => 934378 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/934378
Multiprocessor system for updating status information through flip-flopping read version and write version of checkpoint data Nov 23, 1986 Issued
Array ( [id] => 2755515 [patent_doc_number] => 05012441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Apparatus for addressing memory with data word and data block reversal capability' [patent_app_type] => 1 [patent_app_number] => 6/933815 [patent_app_country] => US [patent_app_date] => 1986-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1617 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/012/05012441.pdf [firstpage_image] =>[orig_patent_app_number] => 933815 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/933815
Apparatus for addressing memory with data word and data block reversal capability Nov 23, 1986 Issued
Array ( [id] => 2561920 [patent_doc_number] => 04807178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-21 [patent_title] => 'Programmable sequence controller having indirect and direct input/output apparatus' [patent_app_type] => 1 [patent_app_number] => 6/930232 [patent_app_country] => US [patent_app_date] => 1986-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3103 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/807/04807178.pdf [firstpage_image] =>[orig_patent_app_number] => 930232 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/930232
Programmable sequence controller having indirect and direct input/output apparatus Nov 12, 1986 Issued
06/929579 MULTIPLE ADDRESS SPACE MAPPING FOR A SHARED MEMORY MULTIPROCESSOR Nov 11, 1986 Abandoned
Array ( [id] => 2422055 [patent_doc_number] => 04787064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-22 [patent_title] => 'Circuit module with interface circuits for connecting to plurality of busses operating in different operating modes' [patent_app_type] => 1 [patent_app_number] => 6/928704 [patent_app_country] => US [patent_app_date] => 1986-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2755 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/787/04787064.pdf [firstpage_image] =>[orig_patent_app_number] => 928704 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/928704
Circuit module with interface circuits for connecting to plurality of busses operating in different operating modes Nov 9, 1986 Issued
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