Search

Thomas C. Lee

Supervisory Patent Examiner (ID: 16006, Phone: (571)272-3667 , Office: P/2115 )

Most Active Art Unit
2302
Art Unit(s)
2302, 2307, 2782, 2182, 2185, 2115, 2317
Total Applications
694
Issued Applications
429
Pending Applications
17
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2352355 [patent_doc_number] => 04649474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-10 [patent_title] => 'Chip topography for a MOS disk memory controller circuit' [patent_app_type] => 1 [patent_app_number] => 6/535374 [patent_app_country] => US [patent_app_date] => 1983-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8294 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 613 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/649/04649474.pdf [firstpage_image] =>[orig_patent_app_number] => 535374 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/535374
Chip topography for a MOS disk memory controller circuit Sep 22, 1983 Issued
06/534313 WORD PROCESSOR CAPABLE OF DISPLAYING A LIST OF TEXTS STORED IN AN EXTERNAL MEMORY Sep 20, 1983 Abandoned
06/533988 METHOD FOR CHECKING STORAGE PROTECTION AND A CIRCUIT FOR CARRYING OUT THE SAME Sep 19, 1983 Abandoned
Array ( [id] => 2300262 [patent_doc_number] => 04652992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-24 [patent_title] => 'Topography of integrated circuit CMOS microprocessor chip' [patent_app_type] => 1 [patent_app_number] => 6/534181 [patent_app_country] => US [patent_app_date] => 1983-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9948 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 515 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/652/04652992.pdf [firstpage_image] =>[orig_patent_app_number] => 534181 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/534181
Topography of integrated circuit CMOS microprocessor chip Sep 19, 1983 Issued
Array ( [id] => 2309570 [patent_doc_number] => 04642791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-02-10 [patent_title] => 'Interface for mailing system peripheral devices' [patent_app_type] => 1 [patent_app_number] => 6/532251 [patent_app_country] => US [patent_app_date] => 1983-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5112 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/642/04642791.pdf [firstpage_image] =>[orig_patent_app_number] => 532251 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/532251
Interface for mailing system peripheral devices Sep 14, 1983 Issued
Array ( [id] => 2269265 [patent_doc_number] => 04580243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-04-01 [patent_title] => 'Circuit for duplex synchronization of asynchronous signals' [patent_app_type] => 1 [patent_app_number] => 6/531986 [patent_app_country] => US [patent_app_date] => 1983-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1672 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/580/04580243.pdf [firstpage_image] =>[orig_patent_app_number] => 531986 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/531986
Circuit for duplex synchronization of asynchronous signals Sep 13, 1983 Issued
06/531114 WORKSTATION TAKEOVER CONTROL Sep 11, 1983 Abandoned
06/530820 PREFETCH VALIDATION Sep 11, 1983 Abandoned
Array ( [id] => 2286997 [patent_doc_number] => 04627018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-12-02 [patent_title] => 'Priority requestor accelerator' [patent_app_type] => 1 [patent_app_number] => 6/530285 [patent_app_country] => US [patent_app_date] => 1983-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3474 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/627/04627018.pdf [firstpage_image] =>[orig_patent_app_number] => 530285 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/530285
Priority requestor accelerator Sep 7, 1983 Issued
Array ( [id] => 2391725 [patent_doc_number] => 04695976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-09-22 [patent_title] => 'Combined electronic table preparation and graph drawing apparatus' [patent_app_type] => 1 [patent_app_number] => 6/530071 [patent_app_country] => US [patent_app_date] => 1983-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2432 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/695/04695976.pdf [firstpage_image] =>[orig_patent_app_number] => 530071 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/530071
Combined electronic table preparation and graph drawing apparatus Sep 6, 1983 Issued
06/528162 SERIAL CHIP SCAN Aug 30, 1983 Abandoned
Array ( [id] => 2304872 [patent_doc_number] => 04682281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-07-21 [patent_title] => 'Data storage unit employing translation lookaside buffer pointer' [patent_app_type] => 1 [patent_app_number] => 6/528094 [patent_app_country] => US [patent_app_date] => 1983-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 20560 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/682/04682281.pdf [firstpage_image] =>[orig_patent_app_number] => 528094 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/528094
Data storage unit employing translation lookaside buffer pointer Aug 29, 1983 Issued
Array ( [id] => 2225582 [patent_doc_number] => 04591982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-05-27 [patent_title] => 'Storage selection override apparatus for a multimicroprocessor implemented data processing system' [patent_app_type] => 1 [patent_app_number] => 6/527053 [patent_app_country] => US [patent_app_date] => 1983-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5447 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/591/04591982.pdf [firstpage_image] =>[orig_patent_app_number] => 527053 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/527053
Storage selection override apparatus for a multimicroprocessor implemented data processing system Aug 28, 1983 Issued
06/527147 MULTIPLE PORT PIPELINED PROCESSOR Aug 28, 1983 Abandoned
Array ( [id] => 2282629 [patent_doc_number] => 04611297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-09-09 [patent_title] => 'Bus grant circuit' [patent_app_type] => 1 [patent_app_number] => 6/524270 [patent_app_country] => US [patent_app_date] => 1983-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2150 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/611/04611297.pdf [firstpage_image] =>[orig_patent_app_number] => 524270 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/524270
Bus grant circuit Aug 17, 1983 Issued
Array ( [id] => 2245578 [patent_doc_number] => 04608632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-08-26 [patent_title] => 'Memory paging system in a microcomputer' [patent_app_type] => 1 [patent_app_number] => 6/522892 [patent_app_country] => US [patent_app_date] => 1983-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2001 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 438 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/608/04608632.pdf [firstpage_image] =>[orig_patent_app_number] => 522892 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/522892
Memory paging system in a microcomputer Aug 11, 1983 Issued
Array ( [id] => 2316751 [patent_doc_number] => 04675808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-06-23 [patent_title] => 'Multiplexed-address interface for addressing memories of various sizes' [patent_app_type] => 1 [patent_app_number] => 6/521401 [patent_app_country] => US [patent_app_date] => 1983-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4586 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/675/04675808.pdf [firstpage_image] =>[orig_patent_app_number] => 521401 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/521401
Multiplexed-address interface for addressing memories of various sizes Aug 7, 1983 Issued
Array ( [id] => 2282319 [patent_doc_number] => 04611274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-09-09 [patent_title] => 'Data transmission system via power supply line' [patent_app_type] => 1 [patent_app_number] => 6/518450 [patent_app_country] => US [patent_app_date] => 1983-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2624 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/611/04611274.pdf [firstpage_image] =>[orig_patent_app_number] => 518450 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/518450
Data transmission system via power supply line Jul 28, 1983 Issued
Array ( [id] => 2263088 [patent_doc_number] => 04618926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-10-21 [patent_title] => 'Buffer storage control system' [patent_app_type] => 1 [patent_app_number] => 6/518698 [patent_app_country] => US [patent_app_date] => 1983-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4316 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/618/04618926.pdf [firstpage_image] =>[orig_patent_app_number] => 518698 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/518698
Buffer storage control system Jul 28, 1983 Issued
06/518599 ODD/EVEN STORAGE IN CACHE MEMORY Jul 28, 1983 Abandoned
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