Thomas C. Lee

Array ( [id] => 6632786 [patent_doc_number] => 20020066045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Redundant power indicator feature' [patent_app_type] => new [patent_app_number] => 09/726778 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2276 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066045.pdf [firstpage_image] =>[orig_patent_app_number] => 09726778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 561955 [patent_doc_number] => 07165134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-16 [patent_title] => 'System for selectively generating real-time interrupts and selectively processing associated data when it has higher priority than currently executing non-real-time operation' [patent_app_type] => utility [patent_app_number] => 09/606839 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1874 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/165/07165134.pdf [firstpage_image] =>[orig_patent_app_number] => 09606839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4100979 [patent_doc_number] => 06163825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method for hot adding a network adapter by identifying and executing the adapter driver based upon the logical board number of the network adapter' [patent_app_type] => 1 [patent_app_number] => 9/275906 [patent_app_country] => US [patent_app_date] => 1999-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11151 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163825.pdf [firstpage_image] =>[orig_patent_app_number] => 275906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549699 [patent_doc_number] => 06374360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method and apparatus for bit-to-bit timing correction of a high speed memory bus' [patent_app_type] => B1 [patent_app_number] => 09/209587 [patent_app_country] => US [patent_app_date] => 1998-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14048 [patent_no_of_claims] => 79 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374360.pdf [firstpage_image] =>[orig_patent_app_number] => 09209587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317478 [patent_doc_number] => 06182169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Tether fastened to personal digital assistant by latch having spring biased manual toggle' [patent_app_type] => 1 [patent_app_number] => 9/187152 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3747 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182169.pdf [firstpage_image] =>[orig_patent_app_number] => 187152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426905 [patent_doc_number] => 06195730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Computer system with storage device mapping input/output processor' [patent_app_type] => 1 [patent_app_number] => 9/122008 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195730.pdf [firstpage_image] =>[orig_patent_app_number] => 122008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374219 [patent_doc_number] => 06202164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Data rate synchronization by frame rate adjustment' [patent_app_type] => 1 [patent_app_number] => 9/109822 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5257 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202164.pdf [firstpage_image] =>[orig_patent_app_number] => 109822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4114366 [patent_doc_number] => 06049843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'System for data communication between disk adapter and disk cartridge drive where adapter controller assigns specific track to formatted data to be sent to drive' [patent_app_type] => 1 [patent_app_number] => 9/059574 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 7181 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049843.pdf [firstpage_image] =>[orig_patent_app_number] => 059574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4120400 [patent_doc_number] => 06052655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'System for converting input/output signals where each amplifier section comprises a storage unit containing information items relating to an associated terminal end' [patent_app_type] => 1 [patent_app_number] => 9/040104 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5376 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052655.pdf [firstpage_image] =>[orig_patent_app_number] => 040104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374903 [patent_doc_number] => 06170055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'System for computer recovery using removable high capacity media' [patent_app_type] => 1 [patent_app_number] => 8/962637 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9900 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170055.pdf [firstpage_image] =>[orig_patent_app_number] => 962637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4379331 [patent_doc_number] => 06192434 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'System for hot swapping a programmable adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals' [patent_app_type] => 1 [patent_app_number] => 8/942311 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11370 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192434.pdf [firstpage_image] =>[orig_patent_app_number] => 942311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374473 [patent_doc_number] => 06170028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method for hot swapping a programmable network adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals' [patent_app_type] => 1 [patent_app_number] => 8/942459 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11145 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170028.pdf [firstpage_image] =>[orig_patent_app_number] => 942459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4400016 [patent_doc_number] => 06304929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method for hot swapping a programmable adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals' [patent_app_type] => 1 [patent_app_number] => 8/942457 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11198 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304929.pdf [firstpage_image] =>[orig_patent_app_number] => 942457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4176426 [patent_doc_number] => 06157970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number' [patent_app_type] => 1 [patent_app_number] => 8/936318 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7308 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157970.pdf [firstpage_image] =>[orig_patent_app_number] => 936318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3993332 [patent_doc_number] => 05918067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Multistage front end processor system which uses either a stand-alone pre-processor or a composite pre-processor composed of serially connected stand-alone processors' [patent_app_type] => 1 [patent_app_number] => 8/916208 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6561 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918067.pdf [firstpage_image] =>[orig_patent_app_number] => 916208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3957818 [patent_doc_number] => 05974262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'System for generating output based on involuntary and voluntary user input without providing output information to induce user to alter involuntary input' [patent_app_type] => 1 [patent_app_number] => 8/911752 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4763 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974262.pdf [firstpage_image] =>[orig_patent_app_number] => 911752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4239827 [patent_doc_number] => 06012107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Hardware control block delivery queues for host adapters and other devices with onboard processors' [patent_app_type] => 1 [patent_app_number] => 8/862143 [patent_app_country] => US [patent_app_date] => 1997-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 10397 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012107.pdf [firstpage_image] =>[orig_patent_app_number] => 862143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3858124 [patent_doc_number] => 05848298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'System having two PC cards in a hinged carrying case with battery compartment within in the hinge section' [patent_app_type] => 1 [patent_app_number] => 8/861097 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4459 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848298.pdf [firstpage_image] =>[orig_patent_app_number] => 861097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3955754 [patent_doc_number] => 05930525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method and apparatus for network interface fetching initial and data burst blocks and segmenting blocks and scheduling blocks compatible for transmission over multiple virtual circuits' [patent_app_type] => 1 [patent_app_number] => 8/846355 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5527 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930525.pdf [firstpage_image] =>[orig_patent_app_number] => 846355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291272 [patent_doc_number] => 06247036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Processor with reconfigurable arithmetic data path' [patent_app_type] => 1 [patent_app_number] => 8/787496 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 27855 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247036.pdf [firstpage_image] =>[orig_patent_app_number] => 787496 [rel_patent_id] =>[rel_patent_doc_number] =>)