Search

Thomas C. Lee

Examiner (ID: 3802)

Most Active Art Unit
2302
Art Unit(s)
2317, 2302, 2185, 2782, 2307, 2115, 2182
Total Applications
694
Issued Applications
429
Pending Applications
17
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9718567 [patent_doc_number] => 20140254265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'Flash Memory Cells, NAND Cell Units, Methods of Forming NAND Cell Units, and Methods of Programming NAND Cell Unit Strings' [patent_app_type] => utility [patent_app_number] => 14/282810 [patent_app_country] => US [patent_app_date] => 2014-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14282810 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/282810
Flash Memory Cells, NAND Cell Units, Methods of Forming NAND Cell Units, and Methods of Programming NAND Cell Unit Strings May 19, 2014 Abandoned
Array ( [id] => 10959618 [patent_doc_number] => 20140362645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => '3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter' [patent_app_type] => utility [patent_app_number] => 14/279405 [patent_app_country] => US [patent_app_date] => 2014-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14765 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14279405 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/279405
3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter May 15, 2014 Abandoned
Array ( [id] => 9718555 [patent_doc_number] => 20140254253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'MEMORY ELEMENT AND MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/278716 [patent_app_country] => US [patent_app_date] => 2014-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13971 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14278716 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/278716
Magnetic memory element and magnetic memory device May 14, 2014 Issued
Array ( [id] => 9640924 [patent_doc_number] => 20140219035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/251448 [patent_app_country] => US [patent_app_date] => 2014-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7971 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14251448 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/251448
SEMICONDUCTOR MEMORY DEVICE Apr 10, 2014 Abandoned
Array ( [id] => 11180442 [patent_doc_number] => 09412436 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-09 [patent_title] => 'Memory elements with soft error upset immunity' [patent_app_type] => utility [patent_app_number] => 14/247075 [patent_app_country] => US [patent_app_date] => 2014-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11365 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14247075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/247075
Memory elements with soft error upset immunity Apr 6, 2014 Issued
Array ( [id] => 11300398 [patent_doc_number] => 09508408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Adjustment of write timing in a memory device' [patent_app_type] => utility [patent_app_number] => 14/243283 [patent_app_country] => US [patent_app_date] => 2014-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7152 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14243283 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/243283
Adjustment of write timing in a memory device Apr 1, 2014 Issued
Array ( [id] => 11043287 [patent_doc_number] => 20160240243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/375748 [patent_app_country] => US [patent_app_date] => 2014-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14375748 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/375748
Semiconductor device Apr 1, 2014 Issued
Array ( [id] => 9770056 [patent_doc_number] => 20140293719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WITH A DELAY LOCKED LOOP CIRCUIT AND A METHOD FOR CONTROLLING AN OPERATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/219181 [patent_app_country] => US [patent_app_date] => 2014-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10102 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219181 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/219181
Semiconductor memory device with a delay locked loop circuit and a method for controlling an operation thereof Mar 18, 2014 Issued
Array ( [id] => 10525360 [patent_doc_number] => 09251877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Semiconductor apparatus for controlling phase difference between input signal and strobe signal' [patent_app_type] => utility [patent_app_number] => 14/193659 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7889 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14193659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/193659
Semiconductor apparatus for controlling phase difference between input signal and strobe signal Feb 27, 2014 Issued
Array ( [id] => 10603825 [patent_doc_number] => 09324394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Strobe signal generation device and memory apparatus using the same' [patent_app_type] => utility [patent_app_number] => 14/188793 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5567 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188793 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188793
Strobe signal generation device and memory apparatus using the same Feb 24, 2014 Issued
Array ( [id] => 9697987 [patent_doc_number] => 20140247671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/187500 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 29180 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14187500 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/187500
Semiconductor memory device Feb 23, 2014 Issued
Array ( [id] => 11194109 [patent_doc_number] => 09424927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Memory system, control system and method of predicting lifetime' [patent_app_type] => utility [patent_app_number] => 14/187668 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6269 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14187668 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/187668
Memory system, control system and method of predicting lifetime Feb 23, 2014 Issued
Array ( [id] => 9684313 [patent_doc_number] => 20140241076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/188118 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11617 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188118 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188118
SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND METHOD OF OPERATING THE SAME Feb 23, 2014 Abandoned
Array ( [id] => 9684306 [patent_doc_number] => 20140241069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'MEMORY SYSTEM AND MEMORY ACCESS METHOD' [patent_app_type] => utility [patent_app_number] => 14/186474 [patent_app_country] => US [patent_app_date] => 2014-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14186474 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/186474
Sequentially accessing memory cells in a memory device Feb 20, 2014 Issued
Array ( [id] => 9915805 [patent_doc_number] => 20150071010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'MEMORY DEVICE WITH A COMMON SOURCE LINE MASKING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/186636 [patent_app_country] => US [patent_app_date] => 2014-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3620 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14186636 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/186636
Memory device with a common source line masking circuit Feb 20, 2014 Issued
Array ( [id] => 9733328 [patent_doc_number] => 20140269037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'MAGNETIC MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/184920 [patent_app_country] => US [patent_app_date] => 2014-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 21961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14184920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/184920
Magnetic memory element and nonvolatile memory device Feb 19, 2014 Issued
Array ( [id] => 9684311 [patent_doc_number] => 20140241073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/184566 [patent_app_country] => US [patent_app_date] => 2014-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14184566 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/184566
Semiconductor device Feb 18, 2014 Issued
Array ( [id] => 10556828 [patent_doc_number] => 09281030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Controlling timing of negative charge injection to generate reliable negative bitline voltage' [patent_app_type] => utility [patent_app_number] => 14/178099 [patent_app_country] => US [patent_app_date] => 2014-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14178099 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/178099
Controlling timing of negative charge injection to generate reliable negative bitline voltage Feb 10, 2014 Issued
Array ( [id] => 10165123 [patent_doc_number] => 09196351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks' [patent_app_type] => utility [patent_app_number] => 14/177210 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 23819 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177210 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/177210
Device including a plurality of memory banks and a pipeline control circuit configured to execute a command on the plurality of memory banks Feb 9, 2014 Issued
Array ( [id] => 9915776 [patent_doc_number] => 20150070981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'MAGNETORESISTANCE ELEMENT AND MAGNETORESISTIVE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/160238 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160238 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/160238
MAGNETORESISTANCE ELEMENT AND MAGNETORESISTIVE MEMORY Jan 20, 2014 Abandoned
Menu