Search

Thomas E. Worden

Examiner (ID: 706)

Most Active Art Unit
3669
Art Unit(s)
3669, 3658, 3663
Total Applications
389
Issued Applications
225
Pending Applications
12
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6829952 [patent_doc_number] => 20030181010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'POWER SEMICONDUCTOR DEVICE HAVING A VOLTAGE SUSTAINING REGION THAT INCLUDES DOPED COLUMNS FORMED WITH A SINGLE ION IMPLANTATION STEP' [patent_app_type] => new [patent_app_number] => 10/103674 [patent_app_country] => US [patent_app_date] => 2002-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3914 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 1 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20030181010.pdf [firstpage_image] =>[orig_patent_app_number] => 10103674 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/103674
Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step Mar 20, 2002 Issued
Array ( [id] => 6834817 [patent_doc_number] => 20030162363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'HDP CVD process for void-free gap fill of a high aspect ratio trench' [patent_app_type] => new [patent_app_number] => 10/080468 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3346 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20030162363.pdf [firstpage_image] =>[orig_patent_app_number] => 10080468 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/080468
HDP CVD process for void-free gap fill of a high aspect ratio trench Feb 21, 2002 Abandoned
Array ( [id] => 1336243 [patent_doc_number] => 06593206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Isolation region forming methods' [patent_app_type] => B2 [patent_app_number] => 10/076684 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 4581 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593206.pdf [firstpage_image] =>[orig_patent_app_number] => 10076684 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076684
Isolation region forming methods Feb 13, 2002 Issued
Array ( [id] => 6205390 [patent_doc_number] => 20020070421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Embedded gettering layer in shallow trench isolation structure' [patent_app_type] => new [patent_app_number] => 10/071921 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3947 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20020070421.pdf [firstpage_image] =>[orig_patent_app_number] => 10071921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/071921
Embedded gettering layer in shallow trench isolation structure Feb 7, 2002 Abandoned
Array ( [id] => 5964587 [patent_doc_number] => 20020089034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Isolating region forming methods' [patent_app_type] => new [patent_app_number] => 10/071456 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4623 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20020089034.pdf [firstpage_image] =>[orig_patent_app_number] => 10071456 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/071456
Isolating region forming methods Feb 7, 2002 Abandoned
Array ( [id] => 6276915 [patent_doc_number] => 20020106839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Thin film transistor and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/061578 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4897 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106839.pdf [firstpage_image] =>[orig_patent_app_number] => 10061578 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061578
Thin film transistor and method for manufacturing the same Jan 30, 2002 Issued
Array ( [id] => 6745232 [patent_doc_number] => 20030022415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Method for manufacturing a semiconductor device haveing a metal-insulator-metal capacitor' [patent_app_type] => new [patent_app_number] => 10/055270 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4902 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022415.pdf [firstpage_image] =>[orig_patent_app_number] => 10055270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/055270
Method and manufacturing a semiconductor device having a metal-insulator-metal capacitor Jan 21, 2002 Issued
Array ( [id] => 5964633 [patent_doc_number] => 20020089061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Semiconductor device for suppressing detachment of conductive layer and method for manufacturing the semiconductor device' [patent_app_type] => new [patent_app_number] => 10/054569 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4561 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20020089061.pdf [firstpage_image] =>[orig_patent_app_number] => 10054569 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/054569
Method for manufacturing semiconductor device for suppressing detachment of conductive layer Jan 21, 2002 Issued
Array ( [id] => 1401864 [patent_doc_number] => 06534379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Linerless shallow trench isolation method' [patent_app_type] => B1 [patent_app_number] => 10/051698 [patent_app_country] => US [patent_app_date] => 2002-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 6890 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534379.pdf [firstpage_image] =>[orig_patent_app_number] => 10051698 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/051698
Linerless shallow trench isolation method Jan 17, 2002 Issued
Array ( [id] => 6016449 [patent_doc_number] => 20020102815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method of manufacturing semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/046813 [patent_app_country] => US [patent_app_date] => 2002-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102815.pdf [firstpage_image] =>[orig_patent_app_number] => 10046813 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/046813
Method of manufacturing semiconductor integrated circuit device Jan 16, 2002 Issued
Array ( [id] => 1302491 [patent_doc_number] => 06624496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer' [patent_app_type] => B2 [patent_app_number] => 10/044991 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 6568 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624496.pdf [firstpage_image] =>[orig_patent_app_number] => 10044991 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044991
Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer Jan 14, 2002 Issued
Array ( [id] => 1063658 [patent_doc_number] => 06849901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Device layer of a silicon-on-insulator structure having vacancy dominated and substantially free of agglomerated vacancy-type defects' [patent_app_type] => utility [patent_app_number] => 10/038084 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 42 [patent_no_of_words] => 20079 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849901.pdf [firstpage_image] =>[orig_patent_app_number] => 10038084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038084
Device layer of a silicon-on-insulator structure having vacancy dominated and substantially free of agglomerated vacancy-type defects Jan 2, 2002 Issued
Array ( [id] => 975498 [patent_doc_number] => 06933228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Method of manufacturing of contact plug in a contact hole on a silicon substrate' [patent_app_type] => utility [patent_app_number] => 10/034228 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 5254 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933228.pdf [firstpage_image] =>[orig_patent_app_number] => 10034228 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034228
Method of manufacturing of contact plug in a contact hole on a silicon substrate Dec 27, 2001 Issued
10/036303 Method for fabricating a MOS transistor having improved total radiation-induced leakage current Dec 27, 2001 Abandoned
Array ( [id] => 6683414 [patent_doc_number] => 20030119278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Substrates bonded with oxide affinity agent and bonding method' [patent_app_type] => new [patent_app_number] => 10/029649 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4416 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119278.pdf [firstpage_image] =>[orig_patent_app_number] => 10029649 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029649
Substrates bonded with oxide affinity agent and bonding method Dec 19, 2001 Abandoned
Array ( [id] => 6668996 [patent_doc_number] => 20030113980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Method for manufacturing and structure of semiconductor assembly with a shallow trench device region' [patent_app_type] => new [patent_app_number] => 10/025580 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3519 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20030113980.pdf [firstpage_image] =>[orig_patent_app_number] => 10025580 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/025580
Method for manufacturing and structure of semiconductor assembly with a shallow trench device region Dec 17, 2001 Abandoned
Array ( [id] => 6696918 [patent_doc_number] => 20030109112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Method of manufacturing and structure of semiconductor device with field oxide structure' [patent_app_type] => new [patent_app_number] => 10/013088 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2692 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20030109112.pdf [firstpage_image] =>[orig_patent_app_number] => 10013088 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/013088
Method of manufacturing and structure of semiconductor device with field oxide structure Dec 6, 2001 Issued
Array ( [id] => 6012342 [patent_doc_number] => 20020100952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Semiconductor device and method of forming isolation area in the semiconductor device' [patent_app_type] => new [patent_app_number] => 09/996570 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1980 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20020100952.pdf [firstpage_image] =>[orig_patent_app_number] => 09996570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996570
Semiconductor device and method of forming isolation area in the semiconductor device Nov 29, 2001 Abandoned
Array ( [id] => 1159581 [patent_doc_number] => 06762470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Fingerprint sensor having a portion of the fluorocarbon polymer physical interface layer amorphized' [patent_app_type] => B2 [patent_app_number] => 09/998868 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 6884 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762470.pdf [firstpage_image] =>[orig_patent_app_number] => 09998868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998868
Fingerprint sensor having a portion of the fluorocarbon polymer physical interface layer amorphized Nov 29, 2001 Issued
Array ( [id] => 1502284 [patent_doc_number] => 06486517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-26 [patent_title] => 'Semiconductor device having shallow trench isolation structure and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/998018 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5237 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486517.pdf [firstpage_image] =>[orig_patent_app_number] => 09998018 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998018
Semiconductor device having shallow trench isolation structure and manufacturing method thereof Nov 28, 2001 Issued
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