Search

Thomas E. Worden

Examiner (ID: 706)

Most Active Art Unit
3669
Art Unit(s)
3669, 3658, 3663
Total Applications
389
Issued Applications
225
Pending Applications
12
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 756281 [patent_doc_number] => 07019364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Semiconductor substrate having pillars within a closed empty space' [patent_app_type] => utility [patent_app_number] => 09/650748 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 101 [patent_no_of_words] => 17153 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/019/07019364.pdf [firstpage_image] =>[orig_patent_app_number] => 09650748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650748
Semiconductor substrate having pillars within a closed empty space Aug 29, 2000 Issued
Array ( [id] => 1507441 [patent_doc_number] => 06440839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Selective air gap insulation' [patent_app_type] => B1 [patent_app_number] => 09/639800 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 3990 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440839.pdf [firstpage_image] =>[orig_patent_app_number] => 09639800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/639800
Selective air gap insulation Aug 16, 2000 Issued
Array ( [id] => 1568425 [patent_doc_number] => 06376893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Trench isolation structure and fabrication method thereof' [patent_app_type] => B1 [patent_app_number] => 09/638866 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3307 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376893.pdf [firstpage_image] =>[orig_patent_app_number] => 09638866 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638866
Trench isolation structure and fabrication method thereof Aug 14, 2000 Issued
Array ( [id] => 1600339 [patent_doc_number] => 06475862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Semiconductor device having gate insulating layers different in thickness and material and process for fabrication thereof' [patent_app_type] => B1 [patent_app_number] => 09/636078 [patent_app_country] => US [patent_app_date] => 2000-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 94 [patent_no_of_words] => 7121 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475862.pdf [firstpage_image] =>[orig_patent_app_number] => 09636078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/636078
Semiconductor device having gate insulating layers different in thickness and material and process for fabrication thereof Aug 9, 2000 Issued
Array ( [id] => 774887 [patent_doc_number] => 07002256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-21 [patent_title] => 'Semiconductor device having wiring patterns and dummy patterns covered with insulating layer' [patent_app_type] => utility [patent_app_number] => 09/625178 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4396 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002256.pdf [firstpage_image] =>[orig_patent_app_number] => 09625178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625178
Semiconductor device having wiring patterns and dummy patterns covered with insulating layer Jul 24, 2000 Issued
Array ( [id] => 1093903 [patent_doc_number] => 06825522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Capacitor electrode having an interface layer of different chemical composition formed on a bulk layer' [patent_app_type] => B1 [patent_app_number] => 09/615549 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4885 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825522.pdf [firstpage_image] =>[orig_patent_app_number] => 09615549 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/615549
Capacitor electrode having an interface layer of different chemical composition formed on a bulk layer Jul 12, 2000 Issued
Array ( [id] => 1210930 [patent_doc_number] => 06713847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method of fabricating semiconductor device, and semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/610148 [patent_app_country] => US [patent_app_date] => 2000-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4543 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713847.pdf [firstpage_image] =>[orig_patent_app_number] => 09610148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/610148
Method of fabricating semiconductor device, and semiconductor device Jul 4, 2000 Issued
Array ( [id] => 1594400 [patent_doc_number] => 06383877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer' [patent_app_type] => B1 [patent_app_number] => 09/573268 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 6541 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383877.pdf [firstpage_image] =>[orig_patent_app_number] => 09573268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/573268
Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer May 17, 2000 Issued
Array ( [id] => 1446543 [patent_doc_number] => 06368904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/566480 [patent_app_country] => US [patent_app_date] => 2000-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 34 [patent_no_of_words] => 8059 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368904.pdf [firstpage_image] =>[orig_patent_app_number] => 09566480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/566480
Semiconductor device and method of manufacturing the same May 7, 2000 Issued
Array ( [id] => 4420308 [patent_doc_number] => 06225188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Self aligned method for differential oxidation rate at shallow trench isolation edge' [patent_app_type] => 1 [patent_app_number] => 9/524447 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4693 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225188.pdf [firstpage_image] =>[orig_patent_app_number] => 524447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/524447
Self aligned method for differential oxidation rate at shallow trench isolation edge Mar 13, 2000 Issued
Array ( [id] => 1254327 [patent_doc_number] => 06670690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Method of making an improved field oxide isolation structure for semiconductor integrated circuits having higher field oxide threshold voltages' [patent_app_type] => B1 [patent_app_number] => 09/524519 [patent_app_country] => US [patent_app_date] => 2000-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3247 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670690.pdf [firstpage_image] =>[orig_patent_app_number] => 09524519 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/524519
Method of making an improved field oxide isolation structure for semiconductor integrated circuits having higher field oxide threshold voltages Mar 12, 2000 Issued
Array ( [id] => 4407385 [patent_doc_number] => 06238999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Isolation region forming methods' [patent_app_type] => 1 [patent_app_number] => 9/520288 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 4537 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238999.pdf [firstpage_image] =>[orig_patent_app_number] => 520288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520288
Isolation region forming methods Mar 6, 2000 Issued
Array ( [id] => 4325031 [patent_doc_number] => 06329267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Isolation region forming methods' [patent_app_type] => 1 [patent_app_number] => 9/520739 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 4537 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329267.pdf [firstpage_image] =>[orig_patent_app_number] => 520739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520739
Isolation region forming methods Mar 6, 2000 Issued
09/490459 Wavy-shaped deep trench and method of forming Jan 24, 2000 Abandoned
Array ( [id] => 1520712 [patent_doc_number] => 06413843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method of forming a semiconductor memory device having source/drain diffusion layers with a reduced resistance' [patent_app_type] => B1 [patent_app_number] => 09/487989 [patent_app_country] => US [patent_app_date] => 2000-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 88 [patent_no_of_words] => 11138 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413843.pdf [firstpage_image] =>[orig_patent_app_number] => 09487989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/487989
Method of forming a semiconductor memory device having source/drain diffusion layers with a reduced resistance Jan 19, 2000 Issued
Array ( [id] => 1192995 [patent_doc_number] => 06730579 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method of manufacturing a semiconductor dice by partially dicing the substrate and subsequent chemical etching' [patent_app_type] => B1 [patent_app_number] => 09/487259 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 56 [patent_no_of_words] => 14192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730579.pdf [firstpage_image] =>[orig_patent_app_number] => 09487259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/487259
Method of manufacturing a semiconductor dice by partially dicing the substrate and subsequent chemical etching Jan 18, 2000 Issued
Array ( [id] => 1588856 [patent_doc_number] => 06482716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Uniform recess depth of recessed resist layers in trench structure' [patent_app_type] => B1 [patent_app_number] => 09/481769 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2035 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482716.pdf [firstpage_image] =>[orig_patent_app_number] => 09481769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481769
Uniform recess depth of recessed resist layers in trench structure Jan 10, 2000 Issued
09/479329 Isolation structure for ic featuring grown and buried field oxide Jan 5, 2000 Abandoned
Array ( [id] => 6044418 [patent_doc_number] => 20020167073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'SEMICONDUCTOR DEVICE WITH ANALYSIS PREVENTION FEATURE' [patent_app_type] => new [patent_app_number] => 09/468108 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3415 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20020167073.pdf [firstpage_image] =>[orig_patent_app_number] => 09468108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468108
SEMICONDUCTOR DEVICE WITH ANALYSIS PREVENTION FEATURE Dec 20, 1999 Abandoned
Array ( [id] => 1346806 [patent_doc_number] => 06583069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Method of silicon oxide and silicon glass films deposition' [patent_app_type] => B1 [patent_app_number] => 09/458729 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5275 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583069.pdf [firstpage_image] =>[orig_patent_app_number] => 09458729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458729
Method of silicon oxide and silicon glass films deposition Dec 12, 1999 Issued
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