Search

Thomas E. Worden

Examiner (ID: 706)

Most Active Art Unit
3669
Art Unit(s)
3669, 3658, 3663
Total Applications
389
Issued Applications
225
Pending Applications
12
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4249413 [patent_doc_number] => 06207481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Thin film transistor having a crystallization seed layer and a method for manufacturing thereof' [patent_app_type] => 1 [patent_app_number] => 9/458468 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 7258 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207481.pdf [firstpage_image] =>[orig_patent_app_number] => 458468 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458468
Thin film transistor having a crystallization seed layer and a method for manufacturing thereof Dec 8, 1999 Issued
Array ( [id] => 1602620 [patent_doc_number] => 06432799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of manufacturing semiconductor integrated circuit device' [patent_app_type] => B1 [patent_app_number] => 09/448979 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 9963 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432799.pdf [firstpage_image] =>[orig_patent_app_number] => 09448979 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448979
Method of manufacturing semiconductor integrated circuit device Nov 23, 1999 Issued
09/423969 SUBTRATE FOR PATTERNING THIN FILM AND SURFACE TREATMENT THEREOF Nov 16, 1999 Abandoned
Array ( [id] => 1027971 [patent_doc_number] => 06881687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-19 [patent_title] => 'Method for laser cleaning of a substrate surface using a solid sacrificial film' [patent_app_type] => utility [patent_app_number] => 09/429869 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9642 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/881/06881687.pdf [firstpage_image] =>[orig_patent_app_number] => 09429869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/429869
Method for laser cleaning of a substrate surface using a solid sacrificial film Oct 28, 1999 Issued
Array ( [id] => 1576255 [patent_doc_number] => 06469330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Process for manufacturing integrated devices comprising microstructures and associated suspended electrical interconnections' [patent_app_type] => B1 [patent_app_number] => 09/422049 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2207 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469330.pdf [firstpage_image] =>[orig_patent_app_number] => 09422049 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422049
Process for manufacturing integrated devices comprising microstructures and associated suspended electrical interconnections Oct 19, 1999 Issued
Array ( [id] => 4182437 [patent_doc_number] => 06150237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method of fabricating STI' [patent_app_type] => 1 [patent_app_number] => 9/420049 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2305 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150237.pdf [firstpage_image] =>[orig_patent_app_number] => 420049 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/420049
Method of fabricating STI Oct 17, 1999 Issued
Array ( [id] => 4183363 [patent_doc_number] => 06159823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Trench isolation method of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/404209 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5570 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159823.pdf [firstpage_image] =>[orig_patent_app_number] => 404209 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/404209
Trench isolation method of semiconductor device Sep 22, 1999 Issued
Array ( [id] => 4285516 [patent_doc_number] => 06210989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Ultra thin surface mount wafer sensor structures and methods for fabricating same' [patent_app_type] => 1 [patent_app_number] => 9/398969 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4704 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/210/06210989.pdf [firstpage_image] =>[orig_patent_app_number] => 398969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398969
Ultra thin surface mount wafer sensor structures and methods for fabricating same Sep 16, 1999 Issued
Array ( [id] => 4259275 [patent_doc_number] => 06258696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'System and method for fabricating semiconductor device and isolation structure thereof' [patent_app_type] => 1 [patent_app_number] => 9/396449 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 3723 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258696.pdf [firstpage_image] =>[orig_patent_app_number] => 396449 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396449
System and method for fabricating semiconductor device and isolation structure thereof Sep 14, 1999 Issued
Array ( [id] => 4309702 [patent_doc_number] => 06316281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method for fabricating a hybrid optical integrated circuit employing SOI optical waveguide' [patent_app_type] => 1 [patent_app_number] => 9/393279 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 5585 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316281.pdf [firstpage_image] =>[orig_patent_app_number] => 393279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/393279
Method for fabricating a hybrid optical integrated circuit employing SOI optical waveguide Sep 9, 1999 Issued
Array ( [id] => 6898588 [patent_doc_number] => 20010046753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'METHOD FOR FORMING A SELF-ALIGNED ISOLATION TRENCH' [patent_app_type] => new [patent_app_number] => 09/392034 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6051 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046753.pdf [firstpage_image] =>[orig_patent_app_number] => 09392034 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392034
Method for forming a self-aligned T-shaped isolation trench Sep 7, 1999 Issued
Array ( [id] => 5964585 [patent_doc_number] => 20020089032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'PROCESSING METHOD FOR FORMING DISLOCATION-FREE SILICON-ON-INSULATOR SUBSTRATE PREPARED BY IMPLANTATION OF OXYGEN' [patent_app_type] => new [patent_app_number] => 09/379058 [patent_app_country] => US [patent_app_date] => 1999-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2401 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20020089032.pdf [firstpage_image] =>[orig_patent_app_number] => 09379058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/379058
PROCESSING METHOD FOR FORMING DISLOCATION-FREE SILICON-ON-INSULATOR SUBSTRATE PREPARED BY IMPLANTATION OF OXYGEN Aug 22, 1999 Abandoned
Array ( [id] => 5801606 [patent_doc_number] => 20020009845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'SIMPLIFIED METHOD OF PATTERNING FIELD DIELECTRIC REGIONS IN A SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/376059 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3081 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20020009845.pdf [firstpage_image] =>[orig_patent_app_number] => 09376059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376059
SIMPLIFIED METHOD OF PATTERNING FIELD DIELECTRIC REGIONS IN A SEMICONDUCTOR DEVICE Aug 16, 1999 Abandoned
Array ( [id] => 1494279 [patent_doc_number] => 06342432 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Shallow trench isolation formation without planarization mask' [patent_app_type] => B1 [patent_app_number] => 09/371919 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2708 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342432.pdf [firstpage_image] =>[orig_patent_app_number] => 09371919 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371919
Shallow trench isolation formation without planarization mask Aug 10, 1999 Issued
09/371678 FABRICATION METHOD OF SHALLOW TRENCH ISOLATION Aug 9, 1999 Abandoned
Array ( [id] => 1108996 [patent_doc_number] => 06809395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Isolation structure having trench structures formed on both side of a locos' [patent_app_type] => B1 [patent_app_number] => 09/369579 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6003 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/809/06809395.pdf [firstpage_image] =>[orig_patent_app_number] => 09369579 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/369579
Isolation structure having trench structures formed on both side of a locos Aug 5, 1999 Issued
Array ( [id] => 4356658 [patent_doc_number] => 06190935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Low-cost, high-density light-emitting-diode array and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/359789 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 128 [patent_no_of_words] => 12566 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 442 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190935.pdf [firstpage_image] =>[orig_patent_app_number] => 359789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359789
Low-cost, high-density light-emitting-diode array and fabrication method thereof Jul 25, 1999 Issued
Array ( [id] => 4405639 [patent_doc_number] => 06232203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Process for making improved shallow trench isolation by employing nitride spacers in the formation of the trenches' [patent_app_type] => 1 [patent_app_number] => 9/360119 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 1550 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232203.pdf [firstpage_image] =>[orig_patent_app_number] => 360119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360119
Process for making improved shallow trench isolation by employing nitride spacers in the formation of the trenches Jul 22, 1999 Issued
Array ( [id] => 990734 [patent_doc_number] => 06919260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-19 [patent_title] => 'Method of manufacturing a substrate having shallow trench isolation' [patent_app_type] => utility [patent_app_number] => 09/358388 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 37 [patent_no_of_words] => 11628 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/919/06919260.pdf [firstpage_image] =>[orig_patent_app_number] => 09358388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/358388
Method of manufacturing a substrate having shallow trench isolation Jul 20, 1999 Issued
Array ( [id] => 4302762 [patent_doc_number] => 06187649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Shallow trench isolation process' [patent_app_type] => 1 [patent_app_number] => 9/348409 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 1689 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187649.pdf [firstpage_image] =>[orig_patent_app_number] => 348409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348409
Shallow trench isolation process Jul 6, 1999 Issued
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