Search

Thomas E. Worden

Examiner (ID: 706)

Most Active Art Unit
3669
Art Unit(s)
3669, 3658, 3663
Total Applications
389
Issued Applications
225
Pending Applications
12
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
09/244637 SEMICONDUCTOR DEVICE HAVING A TRENCH-ISOLATED STRUCTURE WITH A SILICON OXY-NITRIDE AT A HIGHER LEVEL THAN A MAIN SURFACE, AND A METHOD OF FABRICATING THE SAME Feb 3, 1999 Abandoned
Array ( [id] => 4344311 [patent_doc_number] => 06284621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Semiconductor structure with a dielectric layer and its producing method' [patent_app_type] => 1 [patent_app_number] => 9/239000 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1938 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284621.pdf [firstpage_image] =>[orig_patent_app_number] => 239000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/239000
Semiconductor structure with a dielectric layer and its producing method Jan 26, 1999 Issued
09/236489 SHALLOW TRENCH ISOLATION PLANARIZED BY WET ETCHBACK AND CHEMICAL MECHANICAL POLISHING Jan 24, 1999 Abandoned
Array ( [id] => 7028178 [patent_doc_number] => 20010014513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'STI DIVOT AND SEAM ELIMINATION' [patent_app_type] => new [patent_app_number] => 09/233888 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2479 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014513.pdf [firstpage_image] =>[orig_patent_app_number] => 09233888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233888
STI DIVOT AND SEAM ELIMINATION Jan 19, 1999 Abandoned
Array ( [id] => 4417297 [patent_doc_number] => 06194288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Implant N2 into a pad oxide film to mask the active region and grow field oxide without Si3N4 film' [patent_app_type] => 1 [patent_app_number] => 9/224719 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1451 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194288.pdf [firstpage_image] =>[orig_patent_app_number] => 224719 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224719
Implant N2 into a pad oxide film to mask the active region and grow field oxide without Si3N4 film Jan 3, 1999 Issued
Array ( [id] => 4381403 [patent_doc_number] => 06261923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local inverse etchback and CMP' [patent_app_type] => 1 [patent_app_number] => 9/225379 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1445 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261923.pdf [firstpage_image] =>[orig_patent_app_number] => 225379 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225379
Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local inverse etchback and CMP Jan 3, 1999 Issued
Array ( [id] => 4354798 [patent_doc_number] => 06200875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer' [patent_app_type] => 1 [patent_app_number] => 9/216788 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2081 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200875.pdf [firstpage_image] =>[orig_patent_app_number] => 216788 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/216788
Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer Dec 20, 1998 Issued
Array ( [id] => 931374 [patent_doc_number] => 06979878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites' [patent_app_type] => utility [patent_app_number] => 09/217213 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4555 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979878.pdf [firstpage_image] =>[orig_patent_app_number] => 09217213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/217213
Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites Dec 20, 1998 Issued
Array ( [id] => 4369030 [patent_doc_number] => 06287939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation' [patent_app_type] => 1 [patent_app_number] => 9/216789 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2054 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287939.pdf [firstpage_image] =>[orig_patent_app_number] => 216789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/216789
Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation Dec 20, 1998 Issued
Array ( [id] => 4358530 [patent_doc_number] => 06255191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method of fabricating an isolation structure in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/215599 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3076 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255191.pdf [firstpage_image] =>[orig_patent_app_number] => 215599 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/215599
Method of fabricating an isolation structure in an integrated circuit Dec 16, 1998 Issued
Array ( [id] => 4154430 [patent_doc_number] => 06103590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'SiC patterning of porous silicon' [patent_app_type] => 1 [patent_app_number] => 9/207939 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4143 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103590.pdf [firstpage_image] =>[orig_patent_app_number] => 207939 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207939
SiC patterning of porous silicon Dec 8, 1998 Issued
Array ( [id] => 4125094 [patent_doc_number] => 06127241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Trench isolation structure and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/195558 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3244 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127241.pdf [firstpage_image] =>[orig_patent_app_number] => 195558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195558
Trench isolation structure and fabrication method thereof Nov 18, 1998 Issued
Array ( [id] => 1469939 [patent_doc_number] => 06407007 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method to solve the delamination of a silicon nitride layer from an underlying spin on glass layer' [patent_app_type] => B1 [patent_app_number] => 09/193669 [patent_app_country] => US [patent_app_date] => 1998-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1905 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407007.pdf [firstpage_image] =>[orig_patent_app_number] => 09193669 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193669
Method to solve the delamination of a silicon nitride layer from an underlying spin on glass layer Nov 16, 1998 Issued
Array ( [id] => 4131723 [patent_doc_number] => 06121130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Laser curing of spin-on dielectric thin films' [patent_app_type] => 1 [patent_app_number] => 9/192338 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121130.pdf [firstpage_image] =>[orig_patent_app_number] => 192338 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192338
Laser curing of spin-on dielectric thin films Nov 15, 1998 Issued
Array ( [id] => 1478027 [patent_doc_number] => 06451644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method of providing a gate conductor with high dopant activation' [patent_app_type] => B1 [patent_app_number] => 09/187618 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451644.pdf [firstpage_image] =>[orig_patent_app_number] => 09187618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187618
Method of providing a gate conductor with high dopant activation Nov 5, 1998 Issued
Array ( [id] => 7636636 [patent_doc_number] => 06380019 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method of manufacturing a transistor with local insulator structure' [patent_app_type] => B1 [patent_app_number] => 09/187498 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 3668 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380019.pdf [firstpage_image] =>[orig_patent_app_number] => 09187498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187498
Method of manufacturing a transistor with local insulator structure Nov 5, 1998 Issued
Array ( [id] => 1327129 [patent_doc_number] => 06599810 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Shallow trench isolation formation with ion implantation' [patent_app_type] => B1 [patent_app_number] => 09/186078 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3865 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599810.pdf [firstpage_image] =>[orig_patent_app_number] => 09186078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186078
Shallow trench isolation formation with ion implantation Nov 4, 1998 Issued
Array ( [id] => 4354795 [patent_doc_number] => 06218316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Planarization of non-planar surfaces in device fabrication' [patent_app_type] => 1 [patent_app_number] => 9/177019 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3043 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218316.pdf [firstpage_image] =>[orig_patent_app_number] => 177019 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/177019
Planarization of non-planar surfaces in device fabrication Oct 21, 1998 Issued
Array ( [id] => 4204789 [patent_doc_number] => 06077748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Advanced trench isolation fabrication scheme for precision polysilicon gate control' [patent_app_type] => 1 [patent_app_number] => 9/174898 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3040 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077748.pdf [firstpage_image] =>[orig_patent_app_number] => 174898 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174898
Advanced trench isolation fabrication scheme for precision polysilicon gate control Oct 18, 1998 Issued
Array ( [id] => 1318249 [patent_doc_number] => 06605497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-12 [patent_title] => 'Method of manufacturing semiconductor device over glass substrate having heat resistance' [patent_app_type] => B2 [patent_app_number] => 09/173567 [patent_app_country] => US [patent_app_date] => 1998-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 52 [patent_no_of_words] => 20027 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/605/06605497.pdf [firstpage_image] =>[orig_patent_app_number] => 09173567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/173567
Method of manufacturing semiconductor device over glass substrate having heat resistance Oct 15, 1998 Issued
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