
Thomas E. Worden
Examiner (ID: 706)
| Most Active Art Unit | 3669 |
| Art Unit(s) | 3669, 3658, 3663 |
| Total Applications | 389 |
| Issued Applications | 225 |
| Pending Applications | 12 |
| Abandoned Applications | 151 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4108237
[patent_doc_number] => 06057251
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Method for forming interlevel dielectric layer in semiconductor device using electron beams'
[patent_app_type] => 1
[patent_app_number] => 9/164938
[patent_app_country] => US
[patent_app_date] => 1998-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2126
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/057/06057251.pdf
[firstpage_image] =>[orig_patent_app_number] => 164938
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164938 | Method for forming interlevel dielectric layer in semiconductor device using electron beams | Sep 30, 1998 | Issued |
Array
(
[id] => 3910989
[patent_doc_number] => 06001708
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Method for fabricating a shallow trench isolation structure using chemical-mechanical polishing'
[patent_app_type] => 1
[patent_app_number] => 9/164288
[patent_app_country] => US
[patent_app_date] => 1998-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2289
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/001/06001708.pdf
[firstpage_image] =>[orig_patent_app_number] => 164288
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164288 | Method for fabricating a shallow trench isolation structure using chemical-mechanical polishing | Sep 30, 1998 | Issued |
Array
(
[id] => 4191136
[patent_doc_number] => 06130119
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'Conductive film-attached substrate and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/160539
[patent_app_country] => US
[patent_app_date] => 1998-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 7372
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/130/06130119.pdf
[firstpage_image] =>[orig_patent_app_number] => 160539
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/160539 | Conductive film-attached substrate and method of manufacturing the same | Sep 24, 1998 | Issued |
Array
(
[id] => 4130285
[patent_doc_number] => 06033971
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Semiconductor device having an element isolating oxide film and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/160379
[patent_app_country] => US
[patent_app_date] => 1998-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 43
[patent_no_of_words] => 7458
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/033/06033971.pdf
[firstpage_image] =>[orig_patent_app_number] => 160379
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/160379 | Semiconductor device having an element isolating oxide film and method of manufacturing the same | Sep 24, 1998 | Issued |
Array
(
[id] => 1542807
[patent_doc_number] => 06372658
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Reducing contamination induced scumming, for semiconductor device, by ashing'
[patent_app_type] => B1
[patent_app_number] => 09/157899
[patent_app_country] => US
[patent_app_date] => 1998-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 2361
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/372/06372658.pdf
[firstpage_image] =>[orig_patent_app_number] => 09157899
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/157899 | Reducing contamination induced scumming, for semiconductor device, by ashing | Sep 20, 1998 | Issued |
Array
(
[id] => 4294219
[patent_doc_number] => 06184104
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Alignment mark strategy for oxide CMP'
[patent_app_type] => 1
[patent_app_number] => 9/151158
[patent_app_country] => US
[patent_app_date] => 1998-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 2775
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 290
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/184/06184104.pdf
[firstpage_image] =>[orig_patent_app_number] => 151158
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/151158 | Alignment mark strategy for oxide CMP | Sep 9, 1998 | Issued |
Array
(
[id] => 1196809
[patent_doc_number] => 06727190
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-27
[patent_title] => 'Method of forming fluorine doped boron-phosphorous silicate glass (F-BPSG) insulating materials'
[patent_app_type] => B2
[patent_app_number] => 09/146839
[patent_app_country] => US
[patent_app_date] => 1998-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2264
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 339
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/727/06727190.pdf
[firstpage_image] =>[orig_patent_app_number] => 09146839
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/146839 | Method of forming fluorine doped boron-phosphorous silicate glass (F-BPSG) insulating materials | Sep 2, 1998 | Issued |
Array
(
[id] => 1542637
[patent_doc_number] => 06372601
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Isolation region forming methods'
[patent_app_type] => B1
[patent_app_number] => 09/146838
[patent_app_country] => US
[patent_app_date] => 1998-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 29
[patent_no_of_words] => 4588
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/372/06372601.pdf
[firstpage_image] =>[orig_patent_app_number] => 09146838
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/146838 | Isolation region forming methods | Sep 2, 1998 | Issued |
Array
(
[id] => 1401846
[patent_doc_number] => 06534378
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Method for forming an integrated circuit device'
[patent_app_type] => B1
[patent_app_number] => 09/143899
[patent_app_country] => US
[patent_app_date] => 1998-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 5973
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/534/06534378.pdf
[firstpage_image] =>[orig_patent_app_number] => 09143899
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143899 | Method for forming an integrated circuit device | Aug 30, 1998 | Issued |
Array
(
[id] => 1486768
[patent_doc_number] => 06365952
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Trench isolation for CMOS devices'
[patent_app_type] => B1
[patent_app_number] => 09/140999
[patent_app_country] => US
[patent_app_date] => 1998-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 19
[patent_no_of_words] => 2803
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/365/06365952.pdf
[firstpage_image] =>[orig_patent_app_number] => 09140999
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/140999 | Trench isolation for CMOS devices | Aug 25, 1998 | Issued |
Array
(
[id] => 4087258
[patent_doc_number] => 06133118
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Edge polysilicon buffer LOCOS isolation'
[patent_app_type] => 1
[patent_app_number] => 9/138298
[patent_app_country] => US
[patent_app_date] => 1998-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2123
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/133/06133118.pdf
[firstpage_image] =>[orig_patent_app_number] => 138298
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/138298 | Edge polysilicon buffer LOCOS isolation | Aug 20, 1998 | Issued |
| 09/136988 | METHOD FOR FORMING INSULATING THIN FILMS | Aug 19, 1998 | Abandoned |
Array
(
[id] => 1411436
[patent_doc_number] => 06524874
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-25
[patent_title] => 'Methods of forming field emission tips using deposited particles as an etch mask'
[patent_app_type] => B1
[patent_app_number] => 09/129978
[patent_app_country] => US
[patent_app_date] => 1998-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3349
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/524/06524874.pdf
[firstpage_image] =>[orig_patent_app_number] => 09129978
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/129978 | Methods of forming field emission tips using deposited particles as an etch mask | Aug 4, 1998 | Issued |
Array
(
[id] => 3944499
[patent_doc_number] => 05998285
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Self-aligned T-shaped process for deep submicron Si MOSFET\'s fabrication'
[patent_app_type] => 1
[patent_app_number] => 9/126199
[patent_app_country] => US
[patent_app_date] => 1998-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 2030
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/998/05998285.pdf
[firstpage_image] =>[orig_patent_app_number] => 126199
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/126199 | Self-aligned T-shaped process for deep submicron Si MOSFET's fabrication | Jul 29, 1998 | Issued |
Array
(
[id] => 4239550
[patent_doc_number] => 06118181
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'System and method for bonding wafers'
[patent_app_type] => 1
[patent_app_number] => 9/124099
[patent_app_country] => US
[patent_app_date] => 1998-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3134
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/118/06118181.pdf
[firstpage_image] =>[orig_patent_app_number] => 124099
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/124099 | System and method for bonding wafers | Jul 28, 1998 | Issued |
Array
(
[id] => 4191367
[patent_doc_number] => 06043146
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Process for forming a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/122709
[patent_app_country] => US
[patent_app_date] => 1998-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 21
[patent_no_of_words] => 4296
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/043/06043146.pdf
[firstpage_image] =>[orig_patent_app_number] => 122709
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/122709 | Process for forming a semiconductor device | Jul 26, 1998 | Issued |
Array
(
[id] => 4191156
[patent_doc_number] => 06043133
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Method of photo alignment for shallow trench isolation chemical-mechanical polishing'
[patent_app_type] => 1
[patent_app_number] => 9/121708
[patent_app_country] => US
[patent_app_date] => 1998-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 4657
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/043/06043133.pdf
[firstpage_image] =>[orig_patent_app_number] => 121708
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121708 | Method of photo alignment for shallow trench isolation chemical-mechanical polishing | Jul 23, 1998 | Issued |
Array
(
[id] => 4099679
[patent_doc_number] => 06066518
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Method of manufacturing semiconductor devices using a crystallization promoting material'
[patent_app_type] => 1
[patent_app_number] => 9/119779
[patent_app_country] => US
[patent_app_date] => 1998-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 34
[patent_no_of_words] => 8103
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/066/06066518.pdf
[firstpage_image] =>[orig_patent_app_number] => 119779
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/119779 | Method of manufacturing semiconductor devices using a crystallization promoting material | Jul 20, 1998 | Issued |
Array
(
[id] => 4197782
[patent_doc_number] => 06013570
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-11
[patent_title] => 'LDD transistor using novel gate trim technique'
[patent_app_type] => 1
[patent_app_number] => 9/118389
[patent_app_country] => US
[patent_app_date] => 1998-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 34
[patent_no_of_words] => 4792
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/013/06013570.pdf
[firstpage_image] =>[orig_patent_app_number] => 118389
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/118389 | LDD transistor using novel gate trim technique | Jul 16, 1998 | Issued |
Array
(
[id] => 4139398
[patent_doc_number] => 06060371
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Process for forming a trench device isolation region on a semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 9/114498
[patent_app_country] => US
[patent_app_date] => 1998-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 13
[patent_no_of_words] => 3474
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/060/06060371.pdf
[firstpage_image] =>[orig_patent_app_number] => 114498
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/114498 | Process for forming a trench device isolation region on a semiconductor substrate | Jul 12, 1998 | Issued |