Search

Thomas G. Bilodeau

Examiner (ID: 16656)

Most Active Art Unit
1107
Art Unit(s)
1107, 2812
Total Applications
354
Issued Applications
289
Pending Applications
4
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3797257 [patent_doc_number] => 05827775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Phase mask laser fabrication of fine pattern electronic interconnect structures' [patent_app_type] => 1 [patent_app_number] => 8/968378 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3450 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/827/05827775.pdf [firstpage_image] =>[orig_patent_app_number] => 968378 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968378
Phase mask laser fabrication of fine pattern electronic interconnect structures Nov 11, 1997 Issued
Array ( [id] => 3826404 [patent_doc_number] => 05759905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening' [patent_app_type] => 1 [patent_app_number] => 8/956918 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2747 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/759/05759905.pdf [firstpage_image] =>[orig_patent_app_number] => 956918 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956918
Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening Oct 22, 1997 Issued
Array ( [id] => 3873289 [patent_doc_number] => 05824597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Method of forming contact hole plug' [patent_app_type] => 1 [patent_app_number] => 8/929372 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 3212 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/824/05824597.pdf [firstpage_image] =>[orig_patent_app_number] => 929372 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929372
Method of forming contact hole plug Sep 14, 1997 Issued
Array ( [id] => 3877560 [patent_doc_number] => 05804501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method for forming a wiring metal layer in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/910037 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2400 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804501.pdf [firstpage_image] =>[orig_patent_app_number] => 910037 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910037
Method for forming a wiring metal layer in a semiconductor device Aug 11, 1997 Issued
Array ( [id] => 3742814 [patent_doc_number] => 05801086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Process for formation of contact conductive layer in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/893739 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1828 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801086.pdf [firstpage_image] =>[orig_patent_app_number] => 893739 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/893739
Process for formation of contact conductive layer in a semiconductor device Jul 10, 1997 Issued
Array ( [id] => 3791818 [patent_doc_number] => 05780357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Deposition process for coating or filling re-entry shaped contact holes' [patent_app_type] => 1 [patent_app_number] => 8/867276 [patent_app_country] => US [patent_app_date] => 1997-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6153 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780357.pdf [firstpage_image] =>[orig_patent_app_number] => 867276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/867276
Deposition process for coating or filling re-entry shaped contact holes Jun 1, 1997 Issued
Array ( [id] => 3832280 [patent_doc_number] => 05712207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Profile improvement of a metal interconnect structure on a tungsten plug' [patent_app_type] => 1 [patent_app_number] => 8/858289 [patent_app_country] => US [patent_app_date] => 1997-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2640 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712207.pdf [firstpage_image] =>[orig_patent_app_number] => 858289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/858289
Profile improvement of a metal interconnect structure on a tungsten plug May 18, 1997 Issued
Array ( [id] => 3881881 [patent_doc_number] => 05798300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Method for forming conductors in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/857079 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 994 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798300.pdf [firstpage_image] =>[orig_patent_app_number] => 857079 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857079
Method for forming conductors in integrated circuits May 14, 1997 Issued
Array ( [id] => 3826418 [patent_doc_number] => 05759906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/827813 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4858 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/759/05759906.pdf [firstpage_image] =>[orig_patent_app_number] => 827813 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827813
Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits Apr 10, 1997 Issued
Array ( [id] => 3833928 [patent_doc_number] => 05707407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Method of forming chip-formed solid electrolytic capacitor without an anode lead projecting from anode member' [patent_app_type] => 1 [patent_app_number] => 8/797315 [patent_app_country] => US [patent_app_date] => 1997-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4192 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/707/05707407.pdf [firstpage_image] =>[orig_patent_app_number] => 797315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797315
Method of forming chip-formed solid electrolytic capacitor without an anode lead projecting from anode member Feb 6, 1997 Issued
Array ( [id] => 3884673 [patent_doc_number] => 05776822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Method for fabricating semiconductor device having titanium silicide film' [patent_app_type] => 1 [patent_app_number] => 8/785279 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5850 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/776/05776822.pdf [firstpage_image] =>[orig_patent_app_number] => 785279 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785279
Method for fabricating semiconductor device having titanium silicide film Jan 22, 1997 Issued
Array ( [id] => 3804711 [patent_doc_number] => 05830801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Resistless methods of gate formation in MOS devices' [patent_app_type] => 1 [patent_app_number] => 8/775909 [patent_app_country] => US [patent_app_date] => 1997-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 1791 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/830/05830801.pdf [firstpage_image] =>[orig_patent_app_number] => 775909 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/775909
Resistless methods of gate formation in MOS devices Jan 1, 1997 Issued
Array ( [id] => 3938415 [patent_doc_number] => 05872053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Method of forming an enlarged head on a plug to eliminate the enclosure requirement' [patent_app_type] => 1 [patent_app_number] => 8/758723 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 6381 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872053.pdf [firstpage_image] =>[orig_patent_app_number] => 758723 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758723
Method of forming an enlarged head on a plug to eliminate the enclosure requirement Dec 29, 1996 Issued
Array ( [id] => 3815637 [patent_doc_number] => 05770515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Method of in-situ wafer cooling for a sequential WSI/alpha -Si sputtering process' [patent_app_type] => 1 [patent_app_number] => 8/764335 [patent_app_country] => US [patent_app_date] => 1996-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1219 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770515.pdf [firstpage_image] =>[orig_patent_app_number] => 764335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/764335
Method of in-situ wafer cooling for a sequential WSI/alpha -Si sputtering process Dec 11, 1996 Issued
Array ( [id] => 3855786 [patent_doc_number] => 05705426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method of forming semiconductor device having planarized wiring with good thermal resistance' [patent_app_type] => 1 [patent_app_number] => 8/757501 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4376 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705426.pdf [firstpage_image] =>[orig_patent_app_number] => 757501 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757501
Method of forming semiconductor device having planarized wiring with good thermal resistance Nov 26, 1996 Issued
Array ( [id] => 3838655 [patent_doc_number] => 05744378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Method for fabricating a semiconductor device having multilevel interconnections' [patent_app_type] => 1 [patent_app_number] => 8/755198 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 3535 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744378.pdf [firstpage_image] =>[orig_patent_app_number] => 755198 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/755198
Method for fabricating a semiconductor device having multilevel interconnections Nov 24, 1996 Issued
Array ( [id] => 3849539 [patent_doc_number] => 05767011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Fabrication method for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/749081 [patent_app_country] => US [patent_app_date] => 1996-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7561 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767011.pdf [firstpage_image] =>[orig_patent_app_number] => 749081 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/749081
Fabrication method for integrated circuits Nov 13, 1996 Issued
Array ( [id] => 3812500 [patent_doc_number] => 05710070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Application of titanium nitride and tungsten nitride thin film resistor for thermal ink jet technology' [patent_app_type] => 1 [patent_app_number] => 8/745637 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710070.pdf [firstpage_image] =>[orig_patent_app_number] => 745637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/745637
Application of titanium nitride and tungsten nitride thin film resistor for thermal ink jet technology Nov 7, 1996 Issued
Array ( [id] => 3826544 [patent_doc_number] => 05759915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method of forming semiconductor device having an improved buried electrode formed by selective CVD' [patent_app_type] => 1 [patent_app_number] => 8/749379 [patent_app_country] => US [patent_app_date] => 1996-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3486 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/759/05759915.pdf [firstpage_image] =>[orig_patent_app_number] => 749379 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/749379
Method of forming semiconductor device having an improved buried electrode formed by selective CVD Nov 5, 1996 Issued
Array ( [id] => 3808249 [patent_doc_number] => 05811352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method of making reliable metal leads in high speed LSI semiconductors using dummy leads' [patent_app_type] => 1 [patent_app_number] => 8/857803 [patent_app_country] => US [patent_app_date] => 1996-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 18 [patent_no_of_words] => 3936 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811352.pdf [firstpage_image] =>[orig_patent_app_number] => 857803 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857803
Method of making reliable metal leads in high speed LSI semiconductors using dummy leads Nov 5, 1996 Issued
Menu