
Thomas G. Bilodeau
Examiner (ID: 16656)
| Most Active Art Unit | 1107 |
| Art Unit(s) | 1107, 2812 |
| Total Applications | 354 |
| Issued Applications | 289 |
| Pending Applications | 4 |
| Abandoned Applications | 61 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3797257
[patent_doc_number] => 05827775
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Phase mask laser fabrication of fine pattern electronic interconnect structures'
[patent_app_type] => 1
[patent_app_number] => 8/968378
[patent_app_country] => US
[patent_app_date] => 1997-11-12
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[patent_maintenance] => 1
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[pdf_file] => patents/05/827/05827775.pdf
[firstpage_image] =>[orig_patent_app_number] => 968378
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/968378 | Phase mask laser fabrication of fine pattern electronic interconnect structures | Nov 11, 1997 | Issued |
Array
(
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[patent_doc_number] => 05759905
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening'
[patent_app_type] => 1
[patent_app_number] => 8/956918
[patent_app_country] => US
[patent_app_date] => 1997-10-23
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Array
(
[id] => 3873289
[patent_doc_number] => 05824597
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[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Method of forming contact hole plug'
[patent_app_type] => 1
[patent_app_number] => 8/929372
[patent_app_country] => US
[patent_app_date] => 1997-09-15
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[firstpage_image] =>[orig_patent_app_number] => 929372
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/929372 | Method of forming contact hole plug | Sep 14, 1997 | Issued |
Array
(
[id] => 3877560
[patent_doc_number] => 05804501
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Method for forming a wiring metal layer in a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/910037
[patent_app_country] => US
[patent_app_date] => 1997-08-12
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[firstpage_image] =>[orig_patent_app_number] => 910037
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/910037 | Method for forming a wiring metal layer in a semiconductor device | Aug 11, 1997 | Issued |
Array
(
[id] => 3742814
[patent_doc_number] => 05801086
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[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Process for formation of contact conductive layer in a semiconductor device'
[patent_app_type] => 1
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[patent_app_date] => 1997-07-11
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[firstpage_image] =>[orig_patent_app_number] => 893739
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/893739 | Process for formation of contact conductive layer in a semiconductor device | Jul 10, 1997 | Issued |
Array
(
[id] => 3791818
[patent_doc_number] => 05780357
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[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Deposition process for coating or filling re-entry shaped contact holes'
[patent_app_type] => 1
[patent_app_number] => 8/867276
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[patent_app_date] => 1997-06-02
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[pdf_file] => patents/05/780/05780357.pdf
[firstpage_image] =>[orig_patent_app_number] => 867276
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/867276 | Deposition process for coating or filling re-entry shaped contact holes | Jun 1, 1997 | Issued |
Array
(
[id] => 3832280
[patent_doc_number] => 05712207
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-27
[patent_title] => 'Profile improvement of a metal interconnect structure on a tungsten plug'
[patent_app_type] => 1
[patent_app_number] => 8/858289
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[patent_app_date] => 1997-05-19
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[pdf_file] => patents/05/712/05712207.pdf
[firstpage_image] =>[orig_patent_app_number] => 858289
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/858289 | Profile improvement of a metal interconnect structure on a tungsten plug | May 18, 1997 | Issued |
Array
(
[id] => 3881881
[patent_doc_number] => 05798300
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Method for forming conductors in integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/857079
[patent_app_country] => US
[patent_app_date] => 1997-05-15
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[pdf_file] => patents/05/798/05798300.pdf
[firstpage_image] =>[orig_patent_app_number] => 857079
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/857079 | Method for forming conductors in integrated circuits | May 14, 1997 | Issued |
Array
(
[id] => 3826418
[patent_doc_number] => 05759906
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/827813
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[patent_app_date] => 1997-04-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/827813 | Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits | Apr 10, 1997 | Issued |
Array
(
[id] => 3833928
[patent_doc_number] => 05707407
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Method of forming chip-formed solid electrolytic capacitor without an anode lead projecting from anode member'
[patent_app_type] => 1
[patent_app_number] => 8/797315
[patent_app_country] => US
[patent_app_date] => 1997-02-07
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[pdf_file] => patents/05/707/05707407.pdf
[firstpage_image] =>[orig_patent_app_number] => 797315
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/797315 | Method of forming chip-formed solid electrolytic capacitor without an anode lead projecting from anode member | Feb 6, 1997 | Issued |
Array
(
[id] => 3884673
[patent_doc_number] => 05776822
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Method for fabricating semiconductor device having titanium silicide film'
[patent_app_type] => 1
[patent_app_number] => 8/785279
[patent_app_country] => US
[patent_app_date] => 1997-01-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/776/05776822.pdf
[firstpage_image] =>[orig_patent_app_number] => 785279
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/785279 | Method for fabricating semiconductor device having titanium silicide film | Jan 22, 1997 | Issued |
Array
(
[id] => 3804711
[patent_doc_number] => 05830801
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Resistless methods of gate formation in MOS devices'
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[patent_app_number] => 8/775909
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[pdf_file] => patents/05/830/05830801.pdf
[firstpage_image] =>[orig_patent_app_number] => 775909
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/775909 | Resistless methods of gate formation in MOS devices | Jan 1, 1997 | Issued |
Array
(
[id] => 3938415
[patent_doc_number] => 05872053
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Method of forming an enlarged head on a plug to eliminate the enclosure requirement'
[patent_app_type] => 1
[patent_app_number] => 8/758723
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[patent_app_date] => 1996-12-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/758723 | Method of forming an enlarged head on a plug to eliminate the enclosure requirement | Dec 29, 1996 | Issued |
Array
(
[id] => 3815637
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[patent_title] => 'Method of in-situ wafer cooling for a sequential WSI/alpha -Si sputtering process'
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Array
(
[id] => 3855786
[patent_doc_number] => 05705426
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[patent_title] => 'Method of forming semiconductor device having planarized wiring with good thermal resistance'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757501 | Method of forming semiconductor device having planarized wiring with good thermal resistance | Nov 26, 1996 | Issued |
Array
(
[id] => 3838655
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[patent_app_number] => 8/755198
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/755198 | Method for fabricating a semiconductor device having multilevel interconnections | Nov 24, 1996 | Issued |
Array
(
[id] => 3849539
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749081 | Fabrication method for integrated circuits | Nov 13, 1996 | Issued |
Array
(
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[patent_title] => 'Application of titanium nitride and tungsten nitride thin film resistor for thermal ink jet technology'
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Array
(
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Array
(
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