| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3596132
[patent_doc_number] => 05578166
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Method of reactive ion etching of a thin copper film'
[patent_app_type] => 1
[patent_app_number] => 8/449340
[patent_app_country] => US
[patent_app_date] => 1995-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 5520
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[patent_words_short_claim] => 129
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/578/05578166.pdf
[firstpage_image] =>[orig_patent_app_number] => 449340
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/449340 | Method of reactive ion etching of a thin copper film | May 23, 1995 | Issued |
| 08/449361 | ELECTROMIGRATION RESISTANT METALLIZATION PROCESS FOR MICROCIRCUIT INTERCONNECTIONS WITH RF-REACTIVELY SPUTTERED TITANIUM TUNGSTEN AND GOLD | May 23, 1995 | Abandoned |
Array
(
[id] => 3524142
[patent_doc_number] => 05527739
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Process for fabricating a semiconductor device having an improved metal interconnect structure'
[patent_app_type] => 1
[patent_app_number] => 8/448157
[patent_app_country] => US
[patent_app_date] => 1995-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4260
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/527/05527739.pdf
[firstpage_image] =>[orig_patent_app_number] => 448157
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/448157 | Process for fabricating a semiconductor device having an improved metal interconnect structure | May 22, 1995 | Issued |
Array
(
[id] => 3524622
[patent_doc_number] => 05504036
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Method of manufacturing semiconductor devices with semiconductor elements formed in a layer of semiconductor material provided on a support slice'
[patent_app_type] => 1
[patent_app_number] => 8/447597
[patent_app_country] => US
[patent_app_date] => 1995-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3481
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/504/05504036.pdf
[firstpage_image] =>[orig_patent_app_number] => 447597
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/447597 | Method of manufacturing semiconductor devices with semiconductor elements formed in a layer of semiconductor material provided on a support slice | May 22, 1995 | Issued |
Array
(
[id] => 3695829
[patent_doc_number] => 05595940
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Method of producing micromechanical structures'
[patent_app_type] => 1
[patent_app_number] => 8/446271
[patent_app_country] => US
[patent_app_date] => 1995-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2766
[patent_no_of_claims] => 9
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[patent_words_short_claim] => 125
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/595/05595940.pdf
[firstpage_image] =>[orig_patent_app_number] => 446271
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/446271 | Method of producing micromechanical structures | May 21, 1995 | Issued |
Array
(
[id] => 3549833
[patent_doc_number] => 05547901
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Method for forming a copper metal wiring with aluminum containing oxidation barrier'
[patent_app_type] => 1
[patent_app_number] => 8/445107
[patent_app_country] => US
[patent_app_date] => 1995-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2276
[patent_no_of_claims] => 13
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[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/547/05547901.pdf
[firstpage_image] =>[orig_patent_app_number] => 445107
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/445107 | Method for forming a copper metal wiring with aluminum containing oxidation barrier | May 18, 1995 | Issued |
| 08/444885 | INTEGRATED CIRCUITS WITH BORDERLESS VIAS | May 18, 1995 | Abandoned |
Array
(
[id] => 3656290
[patent_doc_number] => 05622898
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-22
[patent_title] => 'Process of making an integrated circuit chip composite including parylene coated wire'
[patent_app_type] => 1
[patent_app_number] => 8/445381
[patent_app_country] => US
[patent_app_date] => 1995-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/622/05622898.pdf
[firstpage_image] =>[orig_patent_app_number] => 445381
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/445381 | Process of making an integrated circuit chip composite including parylene coated wire | May 18, 1995 | Issued |
Array
(
[id] => 3875111
[patent_doc_number] => 05747360
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Method of metalizing a semiconductor wafer'
[patent_app_type] => 1
[patent_app_number] => 8/439363
[patent_app_country] => US
[patent_app_date] => 1995-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 12
[patent_no_of_words] => 2043
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/747/05747360.pdf
[firstpage_image] =>[orig_patent_app_number] => 439363
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/439363 | Method of metalizing a semiconductor wafer | May 10, 1995 | Issued |
Array
(
[id] => 3694770
[patent_doc_number] => 05618755
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-08
[patent_title] => 'Method of manufacturing a polycide electrode'
[patent_app_type] => 1
[patent_app_number] => 8/437385
[patent_app_country] => US
[patent_app_date] => 1995-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 18
[patent_no_of_words] => 3623
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/618/05618755.pdf
[firstpage_image] =>[orig_patent_app_number] => 437385
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/437385 | Method of manufacturing a polycide electrode | May 8, 1995 | Issued |
| 08/437865 | METHOD FOR FORMING MULTI-LAYERED METAL WIRING SEMICONDUCTOR ELEMENT | May 8, 1995 | Abandoned |
| 08/436045 | PHASE MASK LASER FABRICATION OF FINE PATTERN ELECTRONIC INTERCONNECT STRUCTURES | May 4, 1995 | Abandoned |
Array
(
[id] => 3546910
[patent_doc_number] => 05545588
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-13
[patent_title] => 'Method of using disposable hard mask for gate critical dimension control'
[patent_app_type] => 1
[patent_app_number] => 8/435189
[patent_app_country] => US
[patent_app_date] => 1995-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2206
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/545/05545588.pdf
[firstpage_image] =>[orig_patent_app_number] => 435189
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/435189 | Method of using disposable hard mask for gate critical dimension control | May 4, 1995 | Issued |
Array
(
[id] => 3528108
[patent_doc_number] => 05582971
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Method of forming submicron contacts'
[patent_app_type] => 1
[patent_app_number] => 8/434371
[patent_app_country] => US
[patent_app_date] => 1995-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1889
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[pdf_file] => patents/05/582/05582971.pdf
[firstpage_image] =>[orig_patent_app_number] => 434371
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/434371 | Method of forming submicron contacts | May 2, 1995 | Issued |
Array
(
[id] => 3608625
[patent_doc_number] => 05509974
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-23
[patent_title] => 'Etch control seal for dissolved wafer process'
[patent_app_type] => 1
[patent_app_number] => 8/434153
[patent_app_country] => US
[patent_app_date] => 1995-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2407
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/509/05509974.pdf
[firstpage_image] =>[orig_patent_app_number] => 434153
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/434153 | Etch control seal for dissolved wafer process | May 1, 1995 | Issued |
| 08/432065 | SEMICONDUCTOR APPARATUS HAVING CONDUCTIVE THIN FILMS AND MANUFACTURING APPARATUS THEREFOR | Apr 30, 1995 | Abandoned |
Array
(
[id] => 3613400
[patent_doc_number] => 05510296
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-23
[patent_title] => 'Manufacturable process for tungsten polycide contacts using amorphous silicon'
[patent_app_type] => 1
[patent_app_number] => 8/429727
[patent_app_country] => US
[patent_app_date] => 1995-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/510/05510296.pdf
[firstpage_image] =>[orig_patent_app_number] => 429727
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/429727 | Manufacturable process for tungsten polycide contacts using amorphous silicon | Apr 26, 1995 | Issued |
Array
(
[id] => 3664685
[patent_doc_number] => 05597763
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Method for manufacturing a semiconductor wiring structure including a self-aligned contact hole'
[patent_app_type] => 1
[patent_app_number] => 8/427855
[patent_app_country] => US
[patent_app_date] => 1995-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/05/597/05597763.pdf
[firstpage_image] =>[orig_patent_app_number] => 427855
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/427855 | Method for manufacturing a semiconductor wiring structure including a self-aligned contact hole | Apr 25, 1995 | Issued |
Array
(
[id] => 3592453
[patent_doc_number] => 05488013
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-30
[patent_title] => 'Method of forming transverse diffusion barrier interconnect structure'
[patent_app_type] => 1
[patent_app_number] => 8/428995
[patent_app_country] => US
[patent_app_date] => 1995-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 25
[patent_no_of_words] => 4523
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/488/05488013.pdf
[firstpage_image] =>[orig_patent_app_number] => 428995
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/428995 | Method of forming transverse diffusion barrier interconnect structure | Apr 25, 1995 | Issued |
| 08/426417 | EFFICIENT ROUTING METHOD AND RESULTING STRUCTURE FOR INTEGRATED CIRCUITS | Apr 17, 1995 | Abandoned |