Thomas G. Bilodeau

Array ( [id] => 3453191 [patent_doc_number] => 05451542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Surface passivation process of compound semiconductor material using UV photosulfidation' [patent_app_type] => 1 [patent_app_number] => 8/263107 [patent_app_country] => US [patent_app_date] => 1994-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2784 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/451/05451542.pdf [firstpage_image] =>[orig_patent_app_number] => 263107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3685805 [patent_doc_number] => 05663098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Method for deposition of a conductor in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/258911 [patent_app_country] => US [patent_app_date] => 1994-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2060 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663098.pdf [firstpage_image] =>[orig_patent_app_number] => 258911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3117385 [patent_doc_number] => 05380671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Method of making non-trenched buried contact for VLSI devices' [patent_app_type] => 1 [patent_app_number] => 8/258717 [patent_app_country] => US [patent_app_date] => 1994-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1653 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/380/05380671.pdf [firstpage_image] =>[orig_patent_app_number] => 258717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3561389 [patent_doc_number] => 05525551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Method for forming insulating film in semiconductor device using a TEOS or HMDS pre-treatment' [patent_app_type] => 1 [patent_app_number] => 8/255727 [patent_app_country] => US [patent_app_date] => 1994-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 4288 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/525/05525551.pdf [firstpage_image] =>[orig_patent_app_number] => 255727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3731121 [patent_doc_number] => 05665640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Method for producing titanium-containing thin films by low temperature plasma-enhanced chemical vapor deposition using a rotating susceptor reactor' [patent_app_type] => 1 [patent_app_number] => 8/253393 [patent_app_country] => US [patent_app_date] => 1994-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 15726 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665640.pdf [firstpage_image] =>[orig_patent_app_number] => 253393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3534509 [patent_doc_number] => 05544773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Method for making multilayer printed circuit board having blind holes and resin-coated copper foil used for the method' [patent_app_type] => 1 [patent_app_number] => 8/252928 [patent_app_country] => US [patent_app_date] => 1994-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 23 [patent_no_of_words] => 16391 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544773.pdf [firstpage_image] =>[orig_patent_app_number] => 252928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3405723 [patent_doc_number] => 05460693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-24 [patent_title] => 'Dry microlithography process' [patent_app_type] => 1 [patent_app_number] => 8/250691 [patent_app_country] => US [patent_app_date] => 1994-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/460/05460693.pdf [firstpage_image] =>[orig_patent_app_number] => 250691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3424615 [patent_doc_number] => 05422288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Method of doping a JFET region in a MOS-gated semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/246307 [patent_app_country] => US [patent_app_date] => 1994-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 1749 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422288.pdf [firstpage_image] =>[orig_patent_app_number] => 246307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3426637 [patent_doc_number] => 05403752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Method for manufacturing a pyrodetector apparatus' [patent_app_type] => 1 [patent_app_number] => 8/242243 [patent_app_country] => US [patent_app_date] => 1994-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3607 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/403/05403752.pdf [firstpage_image] =>[orig_patent_app_number] => 242243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3112258 [patent_doc_number] => 05464794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Method of forming contact openings having concavo-concave shape' [patent_app_type] => 1 [patent_app_number] => 8/241005 [patent_app_country] => US [patent_app_date] => 1994-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 1953 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/464/05464794.pdf [firstpage_image] =>[orig_patent_app_number] => 241005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3592408 [patent_doc_number] => 05488010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Method of fabricating sidewall charge-coupled device with trench isolation' [patent_app_type] => 1 [patent_app_number] => 8/241137 [patent_app_country] => US [patent_app_date] => 1994-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3861 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488010.pdf [firstpage_image] =>[orig_patent_app_number] => 241137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3665711 [patent_doc_number] => 05599746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Method to eliminate polycide peeling at wafer edge using extended scribe lines' [patent_app_type] => 1 [patent_app_number] => 8/239229 [patent_app_country] => US [patent_app_date] => 1994-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1389 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/599/05599746.pdf [firstpage_image] =>[orig_patent_app_number] => 239229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3411106 [patent_doc_number] => 05411913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-02 [patent_title] => 'Simple planarized trench isolation and field oxide formation using poly-silicon' [patent_app_type] => 1 [patent_app_number] => 8/236387 [patent_app_country] => US [patent_app_date] => 1994-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4153 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/411/05411913.pdf [firstpage_image] =>[orig_patent_app_number] => 236387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3574484 [patent_doc_number] => 05523258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Method for avoiding lithographic rounding effects for semiconductor fabrication' [patent_app_type] => 1 [patent_app_number] => 8/235509 [patent_app_country] => US [patent_app_date] => 1994-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 11227 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523258.pdf [firstpage_image] =>[orig_patent_app_number] => 235509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3553232 [patent_doc_number] => 05518967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Process for producing a semiconductor device capable of planarizing a metal film surface thereon' [patent_app_type] => 1 [patent_app_number] => 8/234017 [patent_app_country] => US [patent_app_date] => 1994-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3054 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/518/05518967.pdf [firstpage_image] =>[orig_patent_app_number] => 234017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3495759 [patent_doc_number] => 05532174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Wafer level integrated circuit testing with a sacrificial metal layer' [patent_app_type] => 1 [patent_app_number] => 8/232963 [patent_app_country] => US [patent_app_date] => 1994-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5734 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532174.pdf [firstpage_image] =>[orig_patent_app_number] => 232963 [rel_patent_id] =>[rel_patent_doc_number] =>)