| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3867857
[patent_doc_number] => 05837602
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Method of manufacturing doped interconnect'
[patent_app_type] => 1
[patent_app_number] => 8/743652
[patent_app_country] => US
[patent_app_date] => 1996-11-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/837/05837602.pdf
[firstpage_image] =>[orig_patent_app_number] => 743652
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/743652 | Method of manufacturing doped interconnect | Nov 4, 1996 | Issued |
Array
(
[id] => 3774270
[patent_doc_number] => 05817576
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Utilization of SiH.sub.4 soak and purge in deposition processes'
[patent_app_type] => 1
[patent_app_number] => 8/743929
[patent_app_country] => US
[patent_app_date] => 1996-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/817/05817576.pdf
[firstpage_image] =>[orig_patent_app_number] => 743929
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/743929 | Utilization of SiH.sub.4 soak and purge in deposition processes | Nov 4, 1996 | Issued |
Array
(
[id] => 3812350
[patent_doc_number] => 05710060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-20
[patent_title] => 'Method of forming wiring using sputtered insulating mask'
[patent_app_type] => 1
[patent_app_number] => 8/741471
[patent_app_country] => US
[patent_app_date] => 1996-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3179
[patent_no_of_claims] => 13
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[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/710/05710060.pdf
[firstpage_image] =>[orig_patent_app_number] => 741471
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/741471 | Method of forming wiring using sputtered insulating mask | Oct 29, 1996 | Issued |
Array
(
[id] => 3849588
[patent_doc_number] => 05767014
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Integrated circuit and process for its manufacture'
[patent_app_type] => 1
[patent_app_number] => 8/739133
[patent_app_country] => US
[patent_app_date] => 1996-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 3110
[patent_no_of_claims] => 8
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[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/767/05767014.pdf
[firstpage_image] =>[orig_patent_app_number] => 739133
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/739133 | Integrated circuit and process for its manufacture | Oct 27, 1996 | Issued |
Array
(
[id] => 3769037
[patent_doc_number] => 05849634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'Method of forming silicide film on silicon with oxygen concentration below 10.sup.18 /cm.sup.3'
[patent_app_type] => 1
[patent_app_number] => 8/736907
[patent_app_country] => US
[patent_app_date] => 1996-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 10517
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 102
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/849/05849634.pdf
[firstpage_image] =>[orig_patent_app_number] => 736907
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/736907 | Method of forming silicide film on silicon with oxygen concentration below 10.sup.18 /cm.sup.3 | Oct 24, 1996 | Issued |
Array
(
[id] => 3786265
[patent_doc_number] => 05840625
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Method of fabricating integrated circuit interconnection employing tungsten/aluminum layers'
[patent_app_type] => 1
[patent_app_number] => 8/726443
[patent_app_country] => US
[patent_app_date] => 1996-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/05/840/05840625.pdf
[firstpage_image] =>[orig_patent_app_number] => 726443
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/726443 | Method of fabricating integrated circuit interconnection employing tungsten/aluminum layers | Oct 3, 1996 | Issued |
Array
(
[id] => 3745073
[patent_doc_number] => 05716870
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Method for producing titanium thin films by low temperature plasma-enhanced chemical vapor deposition using a rotating susceptor reactor'
[patent_app_type] => 1
[patent_app_number] => 8/720621
[patent_app_country] => US
[patent_app_date] => 1996-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 15751
[patent_no_of_claims] => 1
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[patent_words_short_claim] => 176
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/716/05716870.pdf
[firstpage_image] =>[orig_patent_app_number] => 720621
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/720621 | Method for producing titanium thin films by low temperature plasma-enhanced chemical vapor deposition using a rotating susceptor reactor | Oct 1, 1996 | Issued |
Array
(
[id] => 3876973
[patent_doc_number] => 05797971
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Method of making composite electrode materials for high energy and high power density energy storage devices'
[patent_app_type] => 1
[patent_app_number] => 8/718883
[patent_app_country] => US
[patent_app_date] => 1996-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4084
[patent_no_of_claims] => 5
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[patent_words_short_claim] => 53
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/797/05797971.pdf
[firstpage_image] =>[orig_patent_app_number] => 718883
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/718883 | Method of making composite electrode materials for high energy and high power density energy storage devices | Sep 23, 1996 | Issued |
Array
(
[id] => 3832114
[patent_doc_number] => 05712195
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-27
[patent_title] => 'Method for making via structure with metallic spacer'
[patent_app_type] => 1
[patent_app_number] => 8/712573
[patent_app_country] => US
[patent_app_date] => 1996-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2912
[patent_no_of_claims] => 4
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[pdf_file] => patents/05/712/05712195.pdf
[firstpage_image] =>[orig_patent_app_number] => 712573
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/712573 | Method for making via structure with metallic spacer | Sep 11, 1996 | Issued |
| 08/710069 | PHASE MASK LASER FABRICATION OF FINE PATTERN ELECTRONIC INTERCONNECT STRUCTURES | Sep 9, 1996 | Abandoned |
Array
(
[id] => 3663590
[patent_doc_number] => 05668051
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-16
[patent_title] => 'Method of forming poly plug to reduce buried contact series resistance'
[patent_app_type] => 1
[patent_app_number] => 8/705453
[patent_app_country] => US
[patent_app_date] => 1996-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/668/05668051.pdf
[firstpage_image] =>[orig_patent_app_number] => 705453
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/705453 | Method of forming poly plug to reduce buried contact series resistance | Aug 28, 1996 | Issued |
Array
(
[id] => 3661176
[patent_doc_number] => 05624871
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'Method for making electrical local interconnects'
[patent_app_type] => 1
[patent_app_number] => 8/699222
[patent_app_country] => US
[patent_app_date] => 1996-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/624/05624871.pdf
[firstpage_image] =>[orig_patent_app_number] => 699222
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/699222 | Method for making electrical local interconnects | Aug 18, 1996 | Issued |
Array
(
[id] => 3870191
[patent_doc_number] => 05763323
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Methods for fabricating integrated circuit devices including etching barrier layers and related structures'
[patent_app_type] => 1
[patent_app_number] => 8/687055
[patent_app_country] => US
[patent_app_date] => 1996-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/763/05763323.pdf
[firstpage_image] =>[orig_patent_app_number] => 687055
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/687055 | Methods for fabricating integrated circuit devices including etching barrier layers and related structures | Aug 6, 1996 | Issued |
| 08/692361 | METHOD OF FORMING A SEMICONDUCTOR METALLIZATION SYSTEM AND STRUCTURE THEREOF | Aug 4, 1996 | Abandoned |
Array
(
[id] => 3841474
[patent_doc_number] => 05707901
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Method utilizing an etch stop layer'
[patent_app_type] => 1
[patent_app_number] => 8/688081
[patent_app_country] => US
[patent_app_date] => 1996-07-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/707/05707901.pdf
[firstpage_image] =>[orig_patent_app_number] => 688081
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/688081 | Method utilizing an etch stop layer | Jul 28, 1996 | Issued |
Array
(
[id] => 3685862
[patent_doc_number] => 05663102
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-02
[patent_title] => 'Method for forming multi-layered metal wiring semiconductor element using cmp or etch back'
[patent_app_type] => 1
[patent_app_number] => 8/688676
[patent_app_country] => US
[patent_app_date] => 1996-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/663/05663102.pdf
[firstpage_image] =>[orig_patent_app_number] => 688676
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/688676 | Method for forming multi-layered metal wiring semiconductor element using cmp or etch back | Jul 28, 1996 | Issued |
Array
(
[id] => 3723549
[patent_doc_number] => 05651858
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-29
[patent_title] => 'Method for forming a tapered opening in silicon'
[patent_app_type] => 1
[patent_app_number] => 8/690192
[patent_app_country] => US
[patent_app_date] => 1996-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[pdf_file] => patents/05/651/05651858.pdf
[firstpage_image] =>[orig_patent_app_number] => 690192
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/690192 | Method for forming a tapered opening in silicon | Jul 25, 1996 | Issued |
Array
(
[id] => 3872904
[patent_doc_number] => 05824568
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Process of making an integrated circuit chip composite'
[patent_app_type] => 1
[patent_app_number] => 8/675822
[patent_app_country] => US
[patent_app_date] => 1996-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/824/05824568.pdf
[firstpage_image] =>[orig_patent_app_number] => 675822
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/675822 | Process of making an integrated circuit chip composite | Jul 4, 1996 | Issued |
| 08/677455 | SLURRY CONTAINING MANGANESE OXIDE AND A FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE USING SUCH A SLURRY | Jul 1, 1996 | Abandoned |
Array
(
[id] => 3731195
[patent_doc_number] => 05665645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Method of manufacturing a semiconductor device using reticles'
[patent_app_type] => 1
[patent_app_number] => 8/668522
[patent_app_country] => US
[patent_app_date] => 1996-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/665/05665645.pdf
[firstpage_image] =>[orig_patent_app_number] => 668522
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/668522 | Method of manufacturing a semiconductor device using reticles | Jun 27, 1996 | Issued |