Search

Thomas G. Bilodeau

Examiner (ID: 19217)

Most Active Art Unit
1107
Art Unit(s)
1107, 2812
Total Applications
354
Issued Applications
289
Pending Applications
4
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3688764 [patent_doc_number] => 05649982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Process for manufacturing super capacitor' [patent_app_type] => 1 [patent_app_number] => 8/631680 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1872 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649982.pdf [firstpage_image] =>[orig_patent_app_number] => 631680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/631680
Process for manufacturing super capacitor Apr 9, 1996 Issued
Array ( [id] => 3838621 [patent_doc_number] => 05744376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Method of manufacturing copper interconnect with top barrier layer' [patent_app_type] => 1 [patent_app_number] => 8/630709 [patent_app_country] => US [patent_app_date] => 1996-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1845 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744376.pdf [firstpage_image] =>[orig_patent_app_number] => 630709 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630709
Method of manufacturing copper interconnect with top barrier layer Apr 7, 1996 Issued
Array ( [id] => 3759837 [patent_doc_number] => 05843835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Damage free gate dielectric process during gate electrode plasma etching' [patent_app_type] => 1 [patent_app_number] => 8/625975 [patent_app_country] => US [patent_app_date] => 1996-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 1951 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843835.pdf [firstpage_image] =>[orig_patent_app_number] => 625975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/625975
Damage free gate dielectric process during gate electrode plasma etching Mar 31, 1996 Issued
Array ( [id] => 3791525 [patent_doc_number] => 05726075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Method for fabricating microbump interconnect for bare semiconductor dice' [patent_app_type] => 1 [patent_app_number] => 8/624991 [patent_app_country] => US [patent_app_date] => 1996-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3850 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726075.pdf [firstpage_image] =>[orig_patent_app_number] => 624991 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/624991
Method for fabricating microbump interconnect for bare semiconductor dice Mar 28, 1996 Issued
Array ( [id] => 3894705 [patent_doc_number] => 05750439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method of making aluminum alloy wiring with less silicon nodule' [patent_app_type] => 1 [patent_app_number] => 8/624873 [patent_app_country] => US [patent_app_date] => 1996-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3086 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/750/05750439.pdf [firstpage_image] =>[orig_patent_app_number] => 624873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/624873
Method of making aluminum alloy wiring with less silicon nodule Mar 26, 1996 Issued
Array ( [id] => 3807789 [patent_doc_number] => 05811319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Methods of forming electrodes on gallium nitride group compound semiconductors' [patent_app_type] => 1 [patent_app_number] => 8/622045 [patent_app_country] => US [patent_app_date] => 1996-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3435 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811319.pdf [firstpage_image] =>[orig_patent_app_number] => 622045 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/622045
Methods of forming electrodes on gallium nitride group compound semiconductors Mar 25, 1996 Issued
Array ( [id] => 3705386 [patent_doc_number] => 05654231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Method of eliminating buried contact trench in SRAM technology' [patent_app_type] => 1 [patent_app_number] => 8/621273 [patent_app_country] => US [patent_app_date] => 1996-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654231.pdf [firstpage_image] =>[orig_patent_app_number] => 621273 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/621273
Method of eliminating buried contact trench in SRAM technology Mar 24, 1996 Issued
Array ( [id] => 4000217 [patent_doc_number] => 05858806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method of bonding IC component to flat panel display' [patent_app_type] => 1 [patent_app_number] => 8/620171 [patent_app_country] => US [patent_app_date] => 1996-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 44 [patent_no_of_words] => 11230 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/858/05858806.pdf [firstpage_image] =>[orig_patent_app_number] => 620171 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/620171
Method of bonding IC component to flat panel display Mar 21, 1996 Issued
Array ( [id] => 3860931 [patent_doc_number] => 05795817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'MOS transistor adopting titanium-carbon-nitride gate electrode and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 8/619361 [patent_app_country] => US [patent_app_date] => 1996-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1532 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/795/05795817.pdf [firstpage_image] =>[orig_patent_app_number] => 619361 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/619361
MOS transistor adopting titanium-carbon-nitride gate electrode and manufacturing method thereof Mar 20, 1996 Issued
Array ( [id] => 3858922 [patent_doc_number] => 05792703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Self-aligned contact wiring process for SI devices' [patent_app_type] => 1 [patent_app_number] => 8/619047 [patent_app_country] => US [patent_app_date] => 1996-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2354 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792703.pdf [firstpage_image] =>[orig_patent_app_number] => 619047 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/619047
Self-aligned contact wiring process for SI devices Mar 19, 1996 Issued
Array ( [id] => 3856009 [patent_doc_number] => 05705441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Ion implant silicon nitride mask for a silicide free contact region in a self aligned silicide process' [patent_app_type] => 1 [patent_app_number] => 8/618177 [patent_app_country] => US [patent_app_date] => 1996-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2247 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705441.pdf [firstpage_image] =>[orig_patent_app_number] => 618177 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/618177
Ion implant silicon nitride mask for a silicide free contact region in a self aligned silicide process Mar 18, 1996 Issued
Array ( [id] => 3813158 [patent_doc_number] => 05789271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method for fabricating microbump interconnect for bare semiconductor dice' [patent_app_type] => 1 [patent_app_number] => 8/617283 [patent_app_country] => US [patent_app_date] => 1996-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3385 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789271.pdf [firstpage_image] =>[orig_patent_app_number] => 617283 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/617283
Method for fabricating microbump interconnect for bare semiconductor dice Mar 17, 1996 Issued
Array ( [id] => 3726969 [patent_doc_number] => 05702980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Method for forming intermetal dielectric with SOG etchback and CMP' [patent_app_type] => 1 [patent_app_number] => 8/616415 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1838 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/702/05702980.pdf [firstpage_image] =>[orig_patent_app_number] => 616415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/616415
Method for forming intermetal dielectric with SOG etchback and CMP Mar 14, 1996 Issued
Array ( [id] => 3739529 [patent_doc_number] => 05753565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Method of reducing overetch during the formation of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/614989 [patent_app_country] => US [patent_app_date] => 1996-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1985 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/753/05753565.pdf [firstpage_image] =>[orig_patent_app_number] => 614989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/614989
Method of reducing overetch during the formation of a semiconductor device Mar 11, 1996 Issued
Array ( [id] => 3731228 [patent_doc_number] => 05665647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Making metal silicide using oxide film' [patent_app_type] => 1 [patent_app_number] => 8/611723 [patent_app_country] => US [patent_app_date] => 1996-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 20 [patent_no_of_words] => 2629 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665647.pdf [firstpage_image] =>[orig_patent_app_number] => 611723 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/611723
Making metal silicide using oxide film Mar 6, 1996 Issued
Array ( [id] => 3858993 [patent_doc_number] => 05792708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for forming residue free patterned polysilicon layers upon high step height integrated circuit substrates' [patent_app_type] => 1 [patent_app_number] => 8/611585 [patent_app_country] => US [patent_app_date] => 1996-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7221 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792708.pdf [firstpage_image] =>[orig_patent_app_number] => 611585 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/611585
Method for forming residue free patterned polysilicon layers upon high step height integrated circuit substrates Mar 5, 1996 Issued
08/612621 THREE DIMENSIONAL CONTACT OR VIA STRUCTURE WITH MULTIPLE SIDEWALL CONTACTS Mar 5, 1996 Abandoned
Array ( [id] => 3759923 [patent_doc_number] => 05843840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Semiconductor device having a wiring layer and method for manufacturing same' [patent_app_type] => 1 [patent_app_number] => 8/610349 [patent_app_country] => US [patent_app_date] => 1996-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 30 [patent_no_of_words] => 6107 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843840.pdf [firstpage_image] =>[orig_patent_app_number] => 610349 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/610349
Semiconductor device having a wiring layer and method for manufacturing same Mar 3, 1996 Issued
Array ( [id] => 3701326 [patent_doc_number] => 05674782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method for efficiently removing by-products produced in dry-etching' [patent_app_type] => 1 [patent_app_number] => 8/611432 [patent_app_country] => US [patent_app_date] => 1996-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3511 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/674/05674782.pdf [firstpage_image] =>[orig_patent_app_number] => 611432 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/611432
Method for efficiently removing by-products produced in dry-etching Mar 3, 1996 Issued
08/608791 PROFILE IMPROVEMENT OF A METAL INTERCONNECT STRUCTURE ON TUNGSTEN PLUG Feb 28, 1996 Abandoned
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