Thomas G. Bilodeau

Array ( [id] => 3649390 [patent_doc_number] => 05605858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Method of forming high-dielectric-constant material electrodes comprising conductive sidewall spacers of same material as electrodes' [patent_app_type] => 1 [patent_app_number] => 8/483804 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 4851 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/605/05605858.pdf [firstpage_image] =>[orig_patent_app_number] => 483804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3665695 [patent_doc_number] => 05599745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Method to provide a void between adjacent conducting lines in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/481051 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3279 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/599/05599745.pdf [firstpage_image] =>[orig_patent_app_number] => 481051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3583256 [patent_doc_number] => 05567209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Method of manufacturing solid electrolytic capacitor' [patent_app_type] => 1 [patent_app_number] => 8/487633 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3275 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/567/05567209.pdf [firstpage_image] =>[orig_patent_app_number] => 487633 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3694915 [patent_doc_number] => 05661087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Vertical interconnect process for silicon segments' [patent_app_type] => 1 [patent_app_number] => 8/476623 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7253 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661087.pdf [firstpage_image] =>[orig_patent_app_number] => 476623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3608046 [patent_doc_number] => 05589417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'TiSi.sub.2 /TiN clad interconnect technology' [patent_app_type] => 1 [patent_app_number] => 8/481665 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1747 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589417.pdf [firstpage_image] =>[orig_patent_app_number] => 481665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3730937 [patent_doc_number] => 05665628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Method of forming conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes' [patent_app_type] => 1 [patent_app_number] => 8/485166 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 6706 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665628.pdf [firstpage_image] =>[orig_patent_app_number] => 485166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3855831 [patent_doc_number] => 05705429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method of manufacturing aluminum wiring at a substrate temperature from 100 to 150 degrees celsius' [patent_app_type] => 1 [patent_app_number] => 8/467846 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3872 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705429.pdf [firstpage_image] =>[orig_patent_app_number] => 467846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3700267 [patent_doc_number] => 05646067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Method of bonding wafers having vias including conductive material' [patent_app_type] => 1 [patent_app_number] => 8/461951 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 55 [patent_no_of_words] => 9753 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646067.pdf [firstpage_image] =>[orig_patent_app_number] => 461951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3807747 [patent_doc_number] => 05811316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method of forming teos oxide and silicon nitride passivation layer on aluminum wiring' [patent_app_type] => 1 [patent_app_number] => 8/460931 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 114 [patent_no_of_words] => 55682 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811316.pdf [firstpage_image] =>[orig_patent_app_number] => 460931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3694727 [patent_doc_number] => 05618752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Method of fabrication of surface mountable integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/462171 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 55 [patent_no_of_words] => 9752 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/618/05618752.pdf [firstpage_image] =>[orig_patent_app_number] => 462171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3506188 [patent_doc_number] => 05569624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Method for shallow junction formation' [patent_app_type] => 1 [patent_app_number] => 8/464021 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3374 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/569/05569624.pdf [firstpage_image] =>[orig_patent_app_number] => 464021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3621499 [patent_doc_number] => 05593924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Use of a capping layer to attain low titanium-silicide sheet resistance and uniform silicide thickness for sub-micron silicon and polysilicon lines' [patent_app_type] => 1 [patent_app_number] => 8/460345 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2013 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593924.pdf [firstpage_image] =>[orig_patent_app_number] => 460345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3612904 [patent_doc_number] => 05534466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Method of making area direct transfer multilayer thin film structure' [patent_app_type] => 1 [patent_app_number] => 8/457191 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3534 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/534/05534466.pdf [firstpage_image] =>[orig_patent_app_number] => 457191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3768728 [patent_doc_number] => 05733805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Method of fabricating semiconductor device utilizing a GaAs single crystal' [patent_app_type] => 1 [patent_app_number] => 8/457569 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2816 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/733/05733805.pdf [firstpage_image] =>[orig_patent_app_number] => 457569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3621489 [patent_doc_number] => 05593923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Method of fabricating semiconductor device having refractory metal silicide layer on impurity region using damage implant and single step anneal' [patent_app_type] => 1 [patent_app_number] => 8/454735 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 32 [patent_no_of_words] => 4259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593923.pdf [firstpage_image] =>[orig_patent_app_number] => 454735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3549819 [patent_doc_number] => 05547900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Method of fabricating a self-aligned contact using a liquid-phase oxide-deposition process' [patent_app_type] => 1 [patent_app_number] => 8/450891 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 1592 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/547/05547900.pdf [firstpage_image] =>[orig_patent_app_number] => 450891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3649783 [patent_doc_number] => 05658355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Method of manufacturing a supercapacitor electrode' [patent_app_type] => 1 [patent_app_number] => 8/450139 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1566 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/658/05658355.pdf [firstpage_image] =>[orig_patent_app_number] => 450139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3690953 [patent_doc_number] => 05604157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Reduced notching of polycide gates using silicon anti reflection layer' [patent_app_type] => 1 [patent_app_number] => 8/450301 [patent_app_country] => US [patent_app_date] => 1995-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2497 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604157.pdf [firstpage_image] =>[orig_patent_app_number] => 450301 [rel_patent_id] =>[rel_patent_doc_number] =>)