Search

Thomas G Wyse

Examiner (ID: 9208)

Most Active Art Unit
1306
Art Unit(s)
2899, 1754, 1724, 1801, 1308, 1306, 3206
Total Applications
1702
Issued Applications
1475
Pending Applications
26
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13347329 [patent_doc_number] => 20180225204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => BUFFER MANAGER [patent_app_type] => utility [patent_app_number] => 15/941660 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941660 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941660
Buffer manager Mar 29, 2018 Issued
Array ( [id] => 13332841 [patent_doc_number] => 20180217958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => Intelligent Connector Module and Bus Control System [patent_app_type] => utility [patent_app_number] => 15/940204 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940204 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/940204
Intelligent Connector Module and Bus Control System Mar 28, 2018 Abandoned
Array ( [id] => 13318633 [patent_doc_number] => 20180210854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => BUS SYSTEM [patent_app_type] => utility [patent_app_number] => 15/928044 [patent_app_country] => US [patent_app_date] => 2018-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15928044 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/928044
Bus system Mar 20, 2018 Issued
Array ( [id] => 13304563 [patent_doc_number] => 20180203818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => INDUSTRIAL DEVICE COMMUNICATION SYSTEM, COMMUNICATION METHOD, AND INDUSTRIAL DEVICE [patent_app_type] => utility [patent_app_number] => 15/920451 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920451 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/920451
Industrial device communication system, communication method, and industrial device Mar 13, 2018 Issued
15/885734 SNAPSHOT-BASED DEDUPLICATION OF DATA IN A STORAGE SYSTEM Jan 30, 2018 Abandoned
Array ( [id] => 12797335 [patent_doc_number] => 20180157614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => SCALABLE DIRECT INTER-NODE COMMUNICATION OVER PERIPHERAL COMPONENT INTERCONNECT-EXPRESS (PCIe) [patent_app_type] => utility [patent_app_number] => 15/885398 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885398 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/885398
Scalable direct inter-node communication over peripheral component interconnect-express (PCIe) Jan 30, 2018 Issued
Array ( [id] => 16271103 [patent_doc_number] => 20200272591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => PORT CIRCUIT, METHOD FOR SUPPLYING POWER FOR ELECTRONIC DEVICE VIA PORT CIRCUIT AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/646075 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16646075 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/646075
PORT CIRCUIT, METHOD FOR SUPPLYING POWER FOR ELECTRONIC DEVICE VIA PORT CIRCUIT AND ELECTRONIC DEVICE Dec 14, 2017 Abandoned
Array ( [id] => 15701211 [patent_doc_number] => 10606782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Aligning received bad data indicators (BDIS) with received data on a cross-chip link [patent_app_type] => utility [patent_app_number] => 15/819655 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6621 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819655
Aligning received bad data indicators (BDIS) with received data on a cross-chip link Nov 20, 2017 Issued
Array ( [id] => 12182466 [patent_doc_number] => 20180041403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'SYSTEM AND METHOD FOR NEGOTIATING CONTROL OF A SHARED AUDIO OR VISUAL RESOURCE' [patent_app_type] => utility [patent_app_number] => 15/785184 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15644 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15785184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/785184
System and method for negotiating control of a shared audio or visual resource Oct 15, 2017 Issued
Array ( [id] => 12611067 [patent_doc_number] => 20180095519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => Method and Apparatus for Disabling High Speed Bus Operation Under High Common Mode Voltage Conditions [patent_app_type] => utility [patent_app_number] => 15/709177 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15709177 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/709177
Method and apparatus for disabling high speed bus operation under high common mode voltage conditions Sep 18, 2017 Issued
Array ( [id] => 15106571 [patent_doc_number] => 10474611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Aligning received bad data indicators (BDIS) with received data on a cross-chip link [patent_app_type] => utility [patent_app_number] => 15/708482 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6600 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708482 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/708482
Aligning received bad data indicators (BDIS) with received data on a cross-chip link Sep 18, 2017 Issued
Array ( [id] => 12647349 [patent_doc_number] => 20180107614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => COMPUTING SYSTEM WITH A NONVOLATILE STORAGE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/709112 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15709112 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/709112
Computing system with a nonvolatile storage and operating method thereof Sep 18, 2017 Issued
Array ( [id] => 16478351 [patent_doc_number] => 10853299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Hot-plugged PCIe device configuration system [patent_app_type] => utility [patent_app_number] => 15/706382 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706382 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706382
Hot-plugged PCIe device configuration system Sep 14, 2017 Issued
Array ( [id] => 14571091 [patent_doc_number] => 20190213152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => SOFTWARE-DEFINED DEVICE INTERFACE SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 16/330677 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16330677 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/330677
Software-defined device interface system and method Sep 4, 2017 Issued
Array ( [id] => 12713383 [patent_doc_number] => 20180129627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => RECEIVER TRAINING DURING A SATA OUT OF BAND SEQUENCE [patent_app_type] => utility [patent_app_number] => 15/694531 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694531 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694531
RECEIVER TRAINING DURING A SATA OUT OF BAND SEQUENCE Aug 31, 2017 Abandoned
Array ( [id] => 13693279 [patent_doc_number] => 20170357594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => TRANSACTIONAL MEMORY THAT IS PROGRAMMABLE TO OUTPUT AN ALERT IF A PREDETERMINED MEMORY WRITE OCCURS [patent_app_type] => utility [patent_app_number] => 15/688937 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/688937
Network interface device that alerts a monitoring processor if configuration of a virtual NID is changed Aug 28, 2017 Issued
Array ( [id] => 13992511 [patent_doc_number] => 20190065413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => BURST-SIZED LINKED LIST ELEMENTS FOR A QUEUE [patent_app_type] => utility [patent_app_number] => 15/686528 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686528 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686528
BURST-SIZED LINKED LIST ELEMENTS FOR A QUEUE Aug 24, 2017 Pending
Array ( [id] => 16216862 [patent_doc_number] => 10732669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Serial peripheral interface and methods of operating same [patent_app_type] => utility [patent_app_number] => 15/667907 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15667907 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/667907
Serial peripheral interface and methods of operating same Aug 2, 2017 Issued
Array ( [id] => 11996281 [patent_doc_number] => 20170300436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'SAN FABRIC ONLINE PATH DIAGNOSTICS' [patent_app_type] => utility [patent_app_number] => 15/642186 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11495 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15642186 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/642186
SAN fabric online path diagnostics Jul 4, 2017 Issued
Array ( [id] => 16232723 [patent_doc_number] => 10740273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Schema to ensure payload validity for communications on an asynchronous channel based bus [patent_app_type] => utility [patent_app_number] => 15/635073 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8560 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635073 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635073
Schema to ensure payload validity for communications on an asynchronous channel based bus Jun 26, 2017 Issued
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