Thomas G Wyse
Examiner (ID: 9208)
Most Active Art Unit | 1306 |
Art Unit(s) | 2899, 1754, 1724, 1801, 1308, 1306, 3206 |
Total Applications | 1702 |
Issued Applications | 1475 |
Pending Applications | 26 |
Abandoned Applications | 201 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 17091774
[patent_doc_number] => 11119964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-14
[patent_title] => Communication device and control method
[patent_app_type] => utility
[patent_app_number] => 15/580511
[patent_app_country] => US
[patent_app_date] => 2016-06-02
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[patent_figures_cnt] => 22
[patent_no_of_words] => 17611
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15580511
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/580511 | Communication device and control method | Jun 1, 2016 | Issued |
Array
(
[id] => 11316455
[patent_doc_number] => 20160352565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-01
[patent_title] => 'MEASUREMENT SYSTEM HAVING A PLURALITY OF SENSORS'
[patent_app_type] => utility
[patent_app_number] => 15/167020
[patent_app_country] => US
[patent_app_date] => 2016-05-27
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[patent_drawing_sheets_cnt] => 4
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/167020 | MEASUREMENT SYSTEM HAVING A PLURALITY OF SENSORS | May 26, 2016 | Abandoned |
Array
(
[id] => 11354598
[patent_doc_number] => 20160373338
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[patent_kind] => A1
[patent_issue_date] => 2016-12-22
[patent_title] => 'STORAGE APPARATUS, CONTROL METHOD, AND CONNECTION DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/164150
[patent_app_country] => US
[patent_app_date] => 2016-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/164150 | STORAGE APPARATUS, CONTROL METHOD, AND CONNECTION DEVICE | May 24, 2016 | Abandoned |
Array
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[id] => 11292609
[patent_doc_number] => 20160342540
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-24
[patent_title] => 'LOW LATENCY MEMORY AND BUS FREQUENCY SCALING BASED UPON HARDWARE MONITORING'
[patent_app_type] => utility
[patent_app_number] => 15/159402
[patent_app_country] => US
[patent_app_date] => 2016-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 9634
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159402
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/159402 | LOW LATENCY MEMORY AND BUS FREQUENCY SCALING BASED UPON HARDWARE MONITORING | May 18, 2016 | Abandoned |
Array
(
[id] => 12060806
[patent_doc_number] => 20170337150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'INFRASTRUCTURE MANAGEMENT SYSTEM WITH SUPPORT FOR BREAKOUT CABLES'
[patent_app_type] => utility
[patent_app_number] => 15/158071
[patent_app_country] => US
[patent_app_date] => 2016-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/158071 | Infrastructure management system with support for breakout cables | May 17, 2016 | Issued |
Array
(
[id] => 11709016
[patent_doc_number] => 20170177515
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-22
[patent_title] => 'ELECTRONIC DEVICE AND METHOD OF DRIVING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/156566
[patent_app_country] => US
[patent_app_date] => 2016-05-17
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[patent_drawing_sheets_cnt] => 8
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/156566 | Electronic device and method of driving the same | May 16, 2016 | Issued |
Array
(
[id] => 12053394
[patent_doc_number] => 20170329737
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[patent_kind] => A1
[patent_issue_date] => 2017-11-16
[patent_title] => 'TWO-WIRE LINE-MULTIPLEXED UART TO FOUR-WIRE HIGH-SPEED UART BRIDGING WITH INTEGRATED FLOW CONTROL'
[patent_app_type] => utility
[patent_app_number] => 15/151682
[patent_app_country] => US
[patent_app_date] => 2016-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/151682 | TWO-WIRE LINE-MULTIPLEXED UART TO FOUR-WIRE HIGH-SPEED UART BRIDGING WITH INTEGRATED FLOW CONTROL | May 10, 2016 | Abandoned |
Array
(
[id] => 12032795
[patent_doc_number] => 20170322894
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'SYNCHRONOUS INPUT/OUTPUT COMPUTER SYSTEM INCLUDING HARDWARE INVALIDATION OF SYNCHRONOUS INPUT/OUTPUT CONTEXT'
[patent_app_type] => utility
[patent_app_number] => 15/149219
[patent_app_country] => US
[patent_app_date] => 2016-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/149219 | Synchronous input/output computer system including hardware invalidation of synchronous input/output context | May 8, 2016 | Issued |
Array
(
[id] => 12032793
[patent_doc_number] => 20170322893
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[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'COMPUTING NODE TO INITIATE AN INTERRUPT FOR A WRITE REQUEST RECEIVED OVER A MEMORY FABRIC CHANNEL'
[patent_app_type] => utility
[patent_app_number] => 15/149462
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[patent_app_date] => 2016-05-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/149462 | COMPUTING NODE TO INITIATE AN INTERRUPT FOR A WRITE REQUEST RECEIVED OVER A MEMORY FABRIC CHANNEL | May 8, 2016 | Abandoned |
Array
(
[id] => 12032798
[patent_doc_number] => 20170322897
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'SYSTEMS AND METHODS FOR PROCESSING A SUBMISSION QUEUE'
[patent_app_type] => utility
[patent_app_number] => 15/148409
[patent_app_country] => US
[patent_app_date] => 2016-05-06
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[patent_drawing_sheets_cnt] => 11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/148409 | SYSTEMS AND METHODS FOR PROCESSING A SUBMISSION QUEUE | May 5, 2016 | Abandoned |
Array
(
[id] => 12032800
[patent_doc_number] => 20170322899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'DYNAMIC PCIE SWITCH RECONFIGURATION MECHANISM'
[patent_app_type] => utility
[patent_app_number] => 15/149032
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/149032 | Dynamic PCIE switch reconfiguration mechanism | May 5, 2016 | Issued |
Array
(
[id] => 15016619
[patent_doc_number] => 10454478
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[patent_kind] => B2
[patent_issue_date] => 2019-10-22
[patent_title] => Communication between integrated circuits
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[patent_app_number] => 15/569722
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Array
(
[id] => 12797332
[patent_doc_number] => 20180157613
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[patent_kind] => A1
[patent_issue_date] => 2018-06-07
[patent_title] => VALUE DOCUMENT HANDLING APPARATUS HAVING A DATA COMMUNICATION SYSTEM AND METHOD FOR DISTRIBUTING SENSOR DATA IN A VALUE DOCUMENT HANDLING APPARATUS
[patent_app_type] => utility
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Array
(
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Array
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Array
(
[id] => 11022389
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[patent_app_number] => 14/982684
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/982684 | Media source device with digital format conversion and methods for use therewith | Dec 28, 2015 | Issued |
Array
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[patent_title] => BUS-DEVICE-FUNCTION ADDRESS SPACE MAPPING
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Array
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