Search

Thomas J. Hiltunen

Examiner (ID: 10915, Phone: (571)272-5525 , Office: P/2842 )

Most Active Art Unit
2849
Art Unit(s)
2816, 2842, 2849
Total Applications
1583
Issued Applications
1244
Pending Applications
94
Abandoned Applications
273

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16630183 [patent_doc_number] => 20210048836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => Power Control Circuit [patent_app_type] => utility [patent_app_number] => 16/979622 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16979622 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/979622
Power control circuit Mar 14, 2019 Issued
Array ( [id] => 14895671 [patent_doc_number] => 20190291601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => VEHICLE POWER SUPPLY SYSTEM WITH REDUNDANCY AND METHOD FOR CONTROLLING THE POWER SUPPLY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/351643 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16351643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/351643
Vehicle power supply system with redundancy and method for controlling the power supply system Mar 12, 2019 Issued
Array ( [id] => 14969955 [patent_doc_number] => 20190312456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => POWER SUPPLY DEVICE [patent_app_type] => utility [patent_app_number] => 16/298386 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298386
Power supply device Mar 10, 2019 Issued
Array ( [id] => 14378637 [patent_doc_number] => 20190163231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD FOR SUPPLYING CLOCK SIGNALS IN SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/265251 [patent_app_country] => US [patent_app_date] => 2019-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16265251 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/265251
Semiconductor integrated circuit, and method for supplying clock signals in semiconductor integrated circuit Jan 31, 2019 Issued
Array ( [id] => 16370765 [patent_doc_number] => 10802516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Apparatus and method of power transmission sensing for stacked devices [patent_app_type] => utility [patent_app_number] => 16/190523 [patent_app_country] => US [patent_app_date] => 2018-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3499 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16190523 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/190523
Apparatus and method of power transmission sensing for stacked devices Nov 13, 2018 Issued
Array ( [id] => 15824645 [patent_doc_number] => 10637526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Radio frequency switching circuit and distributed switches [patent_app_type] => utility [patent_app_number] => 16/168681 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 9654 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168681 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/168681
Radio frequency switching circuit and distributed switches Oct 22, 2018 Issued
Array ( [id] => 16265275 [patent_doc_number] => 10756726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Systems with power transistors, transistors coupled to the gates of the power transistors, and capacitive dividers coupled to the power transistors [patent_app_type] => utility [patent_app_number] => 16/148211 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3001 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148211 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148211
Systems with power transistors, transistors coupled to the gates of the power transistors, and capacitive dividers coupled to the power transistors Sep 30, 2018 Issued
Array ( [id] => 16357170 [patent_doc_number] => 10797692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Integrated circuit device [patent_app_type] => utility [patent_app_number] => 16/146378 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6950 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16146378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/146378
Integrated circuit device Sep 27, 2018 Issued
Array ( [id] => 15719313 [patent_doc_number] => 20200106424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => SEMI DYNAMIC FLOP AND SINGLE STAGE PULSE FLOP WITH SHADOW LATCH AND TRANSPARENCY ON BOTH INPUT DATA EDGES [patent_app_type] => utility [patent_app_number] => 16/143973 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143973 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143973
SEMI DYNAMIC FLOP AND SINGLE STAGE PULSE FLOP WITH SHADOW LATCH AND TRANSPARENCY ON BOTH INPUT DATA EDGES Sep 26, 2018 Abandoned
Array ( [id] => 16149505 [patent_doc_number] => 10707840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Power stage with sequential power transistor gate charging [patent_app_type] => utility [patent_app_number] => 16/142699 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3040 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142699 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/142699
Power stage with sequential power transistor gate charging Sep 25, 2018 Issued
Array ( [id] => 14286703 [patent_doc_number] => 20190140636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => ONE-WAY CONDUCTION DEVICE [patent_app_type] => utility [patent_app_number] => 16/143393 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143393 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143393
One-way conduction device Sep 25, 2018 Issued
Array ( [id] => 17716680 [patent_doc_number] => 11380679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => FET capacitor circuit architectures for tunable load and input matching [patent_app_type] => utility [patent_app_number] => 16/141641 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 11986 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141641 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/141641
FET capacitor circuit architectures for tunable load and input matching Sep 24, 2018 Issued
Array ( [id] => 15689253 [patent_doc_number] => 20200099290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => POLE COMPENSATION IN RECONFIGURABLE POWER CONVERTER [patent_app_type] => utility [patent_app_number] => 16/139507 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139507 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139507
Pole compensation in reconfigurable power converter Sep 23, 2018 Issued
Array ( [id] => 15428595 [patent_doc_number] => 10547238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Electronic device with a charging mechanism [patent_app_type] => utility [patent_app_number] => 16/113037 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6949 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16113037 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/113037
Electronic device with a charging mechanism Aug 26, 2018 Issued
Array ( [id] => 14708501 [patent_doc_number] => 10382020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Ultra-low power static state flip flop [patent_app_type] => utility [patent_app_number] => 16/042194 [patent_app_country] => US [patent_app_date] => 2018-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4205 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16042194 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/042194
Ultra-low power static state flip flop Jul 22, 2018 Issued
Array ( [id] => 15416383 [patent_doc_number] => 20200028514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => CURRENT-STARVING IN TUNABLE-LENGTH DELAY (TLD) CIRCUITS EMPLOYABLE IN ADAPTIVE CLOCK DISTRIBUTION (ACD) SYSTEMS FOR COMPENSATING SUPPLY VOLTAGE DROOPS IN INTEGRATED CIRCUITS (ICs) [patent_app_type] => utility [patent_app_number] => 16/038633 [patent_app_country] => US [patent_app_date] => 2018-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16038633 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/038633
Current-starving in tunable-length delay (TLD) circuits employable in adaptive clock distribution (ACD) systems for compensating supply voltage droops in integrated circuits (ICs) Jul 17, 2018 Issued
Array ( [id] => 14477705 [patent_doc_number] => 20190190505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => DELAY CONTROL CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/039050 [patent_app_country] => US [patent_app_date] => 2018-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039050 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/039050
DELAY CONTROL CIRCUITS Jul 17, 2018 Abandoned
Array ( [id] => 14511361 [patent_doc_number] => 20190199335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => DIGITAL MEASUREMENT CIRCUIT AND MEMORY SYSTEM USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/036030 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16036030 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/036030
Digital measurement circuit and memory system using the same Jul 15, 2018 Issued
Array ( [id] => 16202650 [patent_doc_number] => 10727838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Systems and methods for power conservation in a phase locked loop (PLL) [patent_app_type] => utility [patent_app_number] => 16/035024 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6943 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035024
Systems and methods for power conservation in a phase locked loop (PLL) Jul 12, 2018 Issued
Array ( [id] => 13544305 [patent_doc_number] => 20180323699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => Power Loss Protection Integrated Circuit With Autonomous Capacitor Health Check [patent_app_type] => utility [patent_app_number] => 16/030865 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030865 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030865
Power loss protection integrated circuit with autonomous capacitor health check Jul 9, 2018 Issued
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