Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20009538 [patent_doc_number] => 20250147760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => PROCESSOR AND CONTROL METHOD FOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 19/013344 [patent_app_country] => US [patent_app_date] => 2025-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013344 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/013344
PROCESSOR AND CONTROL METHOD FOR PROCESSOR Jan 7, 2025 Pending
Array ( [id] => 20181123 [patent_doc_number] => 20250265081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => SYSTEMS AND METHODS FOR COMPUTING DOT PRODUCTS OF NIBBLES IN TWO TILE OPERANDS [patent_app_type] => utility [patent_app_number] => 19/005958 [patent_app_country] => US [patent_app_date] => 2024-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19005958 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/005958
SYSTEMS AND METHODS FOR COMPUTING DOT PRODUCTS OF NIBBLES IN TWO TILE OPERANDS Dec 29, 2024 Pending
Array ( [id] => 20070655 [patent_doc_number] => 20250208877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => METHOD FOR INSTRUCTION REWRITING, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/958186 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/958186
Method for instruction rewriting, electronic device, and computer-readable storage medium Nov 24, 2024 Issued
Array ( [id] => 19819070 [patent_doc_number] => 20250077277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => NEURAL NETWORK PROCESSOR CAPABLE OF REUSING MEMORY ADDRESS VALUE [patent_app_type] => utility [patent_app_number] => 18/953180 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 55454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18953180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/953180
NEURAL NETWORK PROCESSOR CAPABLE OF REUSING MEMORY ADDRESS VALUE Nov 19, 2024 Pending
Array ( [id] => 20009547 [patent_doc_number] => 20250147769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => METHOD FOR PROCESSING INSTRUCTION, PROCESSOR, ELECTRONIC APPARATUS AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/935154 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935154 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935154
METHOD FOR PROCESSING INSTRUCTION, PROCESSOR, ELECTRONIC APPARATUS AND STORAGE MEDIUM Oct 31, 2024 Pending
Array ( [id] => 20017966 [patent_doc_number] => 20250156188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => APPARATUS AND METHOD FOR PARALLEL PROCESSING [patent_app_type] => utility [patent_app_number] => 18/930458 [patent_app_country] => US [patent_app_date] => 2024-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18930458 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/930458
APPARATUS AND METHOD FOR PARALLEL PROCESSING Oct 28, 2024 Pending
Array ( [id] => 19891905 [patent_doc_number] => 20250117217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS TO CONVERT TO 16-BIT FLOATING-POINT FORMAT [patent_app_type] => utility [patent_app_number] => 18/925482 [patent_app_country] => US [patent_app_date] => 2024-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18925482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/925482
Systems and methods for performing instructions to convert to 16-bit floating-point format Oct 23, 2024 Issued
Array ( [id] => 19756676 [patent_doc_number] => 20250045241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => Cluster-Based Placement and Routing of Memory Units and Compute Units in a Reconfigurable Computing Grid [patent_app_type] => utility [patent_app_number] => 18/922873 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18922873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/922873
Cluster-based placement and routing of memory units and compute units in a reconfigurable computing grid Oct 21, 2024 Issued
Array ( [id] => 20652925 [patent_doc_number] => 20260104944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => RECONFIGURABLE AND ACCELERATED TRANSCEDENTAL FUNCTIONS [patent_app_type] => utility [patent_app_number] => 18/915190 [patent_app_country] => US [patent_app_date] => 2024-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18915190 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/915190
RECONFIGURABLE AND ACCELERATED TRANSCEDENTAL FUNCTIONS Oct 13, 2024 Pending
Array ( [id] => 20601706 [patent_doc_number] => 20260079715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => Granular Source Read Scheduling for Instruction Execution [patent_app_type] => utility [patent_app_number] => 18/911522 [patent_app_country] => US [patent_app_date] => 2024-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18911522 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/911522
Granular Source Read Scheduling for Instruction Execution Oct 9, 2024 Pending
Array ( [id] => 19891914 [patent_doc_number] => 20250117226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => MIXED-SOURCED DEPENDENCY CONTROL FOR VECTOR INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/906205 [patent_app_country] => US [patent_app_date] => 2024-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18906205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/906205
Mixed-sourced dependency control for vector instructions Oct 3, 2024 Issued
Array ( [id] => 20616706 [patent_doc_number] => 20260086802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => SYNCHRONOUS HARDWARE ACCELERATOR INTERFACE [patent_app_type] => utility [patent_app_number] => 18/897127 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18897127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/897127
SYNCHRONOUS HARDWARE ACCELERATOR INTERFACE Sep 25, 2024 Pending
Array ( [id] => 20690963 [patent_doc_number] => 12621126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => SM3 hash algorithm acceleration processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 18/889148 [patent_app_country] => US [patent_app_date] => 2024-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 16895 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18889148 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/889148
SM3 hash algorithm acceleration processors, methods, systems, and instructions Sep 17, 2024 Issued
Array ( [id] => 20601695 [patent_doc_number] => 20260079704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => ACCELERATING A FULLY HOMOMORPHIC ENCRYPTION (FHE) OPERATION WITH AN ON-CHIP SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/885269 [patent_app_country] => US [patent_app_date] => 2024-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18885269 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/885269
ACCELERATING A FULLY HOMOMORPHIC ENCRYPTION (FHE) OPERATION WITH AN ON-CHIP SYSTOLIC ARRAY Sep 12, 2024 Pending
Array ( [id] => 20587151 [patent_doc_number] => 20260072746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => ADAPTIVE ARCHITECTURE FOR NEAR-MEMORY COMPUTING SHARING INACTIVE IN-MEMORY COMPUTING DEVICES [patent_app_type] => utility [patent_app_number] => 18/883431 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883431 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/883431
ADAPTIVE ARCHITECTURE FOR NEAR-MEMORY COMPUTING SHARING INACTIVE IN-MEMORY COMPUTING DEVICES Sep 11, 2024 Pending
Array ( [id] => 20717001 [patent_doc_number] => 12632252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Memory device and method with processing-in-memory block [patent_app_type] => utility [patent_app_number] => 18/814641 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18814641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/814641
Memory device and method with processing-in-memory block Aug 25, 2024 Issued
Array ( [id] => 19617374 [patent_doc_number] => 20240403054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => LOOK-UP TABLE READ [patent_app_type] => utility [patent_app_number] => 18/805711 [patent_app_country] => US [patent_app_date] => 2024-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/805711
LOOK-UP TABLE READ Aug 14, 2024 Pending
Array ( [id] => 19617435 [patent_doc_number] => 20240403115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => Thread Creation on Local or Remote Compute Elements by a Multi-Threaded, Self-Scheduling Processor [patent_app_type] => utility [patent_app_number] => 18/800423 [patent_app_country] => US [patent_app_date] => 2024-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18800423 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/800423
Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor Aug 11, 2024 Issued
Array ( [id] => 19573764 [patent_doc_number] => 20240378056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME TRACKING [patent_app_type] => utility [patent_app_number] => 18/779980 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779980
STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME TRACKING Jul 21, 2024 Pending
Array ( [id] => 20249752 [patent_doc_number] => 20250298621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => PROCESSOR WITH ONE OR MORE PROGRESSIVE CONSERVATIVE EXECUTION MODES [patent_app_type] => utility [patent_app_number] => 18/773632 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773632
Processor with one or more progressive conservative execution modes Jul 15, 2024 Issued
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