Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18622401 [patent_doc_number] => 11755442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Apparatus and method for multithreading-aware performance monitoring events [patent_app_type] => utility [patent_app_number] => 17/242018 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 16423 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242018
Apparatus and method for multithreading-aware performance monitoring events Apr 26, 2021 Issued
Array ( [id] => 19182969 [patent_doc_number] => 11989560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Method and device for executing instructions to perform artificial intelligence [patent_app_type] => utility [patent_app_number] => 17/224473 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6268 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224473 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224473
Method and device for executing instructions to perform artificial intelligence Apr 6, 2021 Issued
Array ( [id] => 18072715 [patent_doc_number] => 11531549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-20 [patent_title] => System and method for instruction mapping in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 17/218771 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 23163 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218771 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218771
System and method for instruction mapping in an out-of-order processor Mar 30, 2021 Issued
Array ( [id] => 18275992 [patent_doc_number] => 11614936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Systems and methods for performing 16-bit floating-point matrix dot product instructions [patent_app_type] => utility [patent_app_number] => 17/216566 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 47 [patent_no_of_words] => 25238 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216566 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216566
Systems and methods for performing 16-bit floating-point matrix dot product instructions Mar 28, 2021 Issued
Array ( [id] => 19841925 [patent_doc_number] => 12254316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Vector processor architectures [patent_app_type] => utility [patent_app_number] => 17/214646 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 83 [patent_no_of_words] => 34273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214646
Vector processor architectures Mar 25, 2021 Issued
Array ( [id] => 17128543 [patent_doc_number] => 20210303312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => DYNAMIC INSTRUMENTATION VIA USER-LEVEL MECHANISMS [patent_app_type] => utility [patent_app_number] => 17/214558 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214558
Dynamic instrumentation via user-level mechanisms Mar 25, 2021 Issued
Array ( [id] => 16950195 [patent_doc_number] => 20210208887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => BIT STRING OPERATIONS USING A COMPUTING TILE [patent_app_type] => utility [patent_app_number] => 17/212387 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212387
BIT STRING OPERATIONS USING A COMPUTING TILE Mar 24, 2021 Abandoned
Array ( [id] => 17276517 [patent_doc_number] => 20210382715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => ARITHMETIC PROCESSING DEVICE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/203000 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203000
Arithmetic processing device and semiconductor device with improved instruction retry Mar 15, 2021 Issued
Array ( [id] => 19062246 [patent_doc_number] => 11941482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-26 [patent_title] => Operating a quantum processor in a heterogeneous computing architecture [patent_app_type] => utility [patent_app_number] => 17/196692 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11245 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196692 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196692
Operating a quantum processor in a heterogeneous computing architecture Mar 8, 2021 Issued
Array ( [id] => 18386095 [patent_doc_number] => 11656876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Removal of dependent instructions from an execution pipeline [patent_app_type] => utility [patent_app_number] => 17/173058 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173058 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173058
Removal of dependent instructions from an execution pipeline Feb 9, 2021 Issued
Array ( [id] => 16856844 [patent_doc_number] => 20210157589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING 16-BIT FLOATING-POINT VECTOR DOT PRODUCT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/167863 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167863 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167863
Systems and methods for performing 16-bit floating-point vector dot product instructions Feb 3, 2021 Issued
Array ( [id] => 17778612 [patent_doc_number] => 20220244962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => METHOD AND SYSTEM FOR PARALLEL PROCESSING OF TASKS IN MULTIPLE THREAD COMPUTING [patent_app_type] => utility [patent_app_number] => 17/162600 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162600 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162600
Method and system for parallel processing of tasks in multiple thread computing Jan 28, 2021 Issued
Array ( [id] => 17301642 [patent_doc_number] => 20210397481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => ACCELERATOR, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/145958 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145958 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145958
Accelerator, method of operating the same, and electronic device including the same Jan 10, 2021 Issued
Array ( [id] => 18407568 [patent_doc_number] => 20230168921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => NEURAL PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 17/431152 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 55093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17431152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/431152
Neural processing unit Dec 30, 2020 Issued
Array ( [id] => 18204074 [patent_doc_number] => 11586465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Scalable hardware thread scheduler [patent_app_type] => utility [patent_app_number] => 17/138649 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7805 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138649
Scalable hardware thread scheduler Dec 29, 2020 Issued
Array ( [id] => 18303347 [patent_doc_number] => 11625249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Preserving memory ordering between offloaded instructions and non-offloaded instructions [patent_app_type] => utility [patent_app_number] => 17/137140 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137140
Preserving memory ordering between offloaded instructions and non-offloaded instructions Dec 28, 2020 Issued
Array ( [id] => 18189337 [patent_doc_number] => 11579922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Dynamic graphical processing unit register allocation [patent_app_type] => utility [patent_app_number] => 17/136725 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136725
Dynamic graphical processing unit register allocation Dec 28, 2020 Issued
Array ( [id] => 17706810 [patent_doc_number] => 20220206816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => APPARATUS AND METHOD FOR HARDWARE-BASED MEMOIZATION OF FUNCTION CALLS TO REDUCE INSTRUCTION EXECUTION [patent_app_type] => utility [patent_app_number] => 17/133899 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133899
Apparatus and method for hardware-based memoization of function calls to reduce instruction execution Dec 23, 2020 Issued
Array ( [id] => 16794764 [patent_doc_number] => 20210124581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS TO CONVERT TO 16-BIT FLOATING-POINT FORMAT [patent_app_type] => utility [patent_app_number] => 17/133255 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133255 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133255
Systems and methods for performing instructions to convert to 16-bit floating-point format Dec 22, 2020 Issued
Array ( [id] => 16894951 [patent_doc_number] => 11036504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Systems and methods for performing 16-bit floating-point vector dot product instructions [patent_app_type] => utility [patent_app_number] => 17/133396 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 16126 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133396
Systems and methods for performing 16-bit floating-point vector dot product instructions Dec 22, 2020 Issued
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