Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16794763 [patent_doc_number] => 20210124580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS TO CONVERT TO 16-BIT FLOATING-POINT FORMAT [patent_app_type] => utility [patent_app_number] => 17/133078 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133078
Systems and methods for performing instructions to convert to 16-bit floating-point format Dec 22, 2020 Issued
Array ( [id] => 17690358 [patent_doc_number] => 20220197651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => PROCESSING OF DATA BY MULTIPLE GRAPHIC PROCESSING DEVICES [patent_app_type] => utility [patent_app_number] => 17/131633 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131633 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131633
Processing of data by multiple graphic processing devices Dec 21, 2020 Issued
Array ( [id] => 17690357 [patent_doc_number] => 20220197650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => ALTERNATE PATH DECODE FOR HARD-TO-PREDICT BRANCH [patent_app_type] => utility [patent_app_number] => 17/130706 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130706 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130706
Alternate path decode for hard-to-predict branch Dec 21, 2020 Issued
Array ( [id] => 17690368 [patent_doc_number] => 20220197661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => CONTEXT-BASED MEMORY INDIRECT BRANCH TARGET PREDICTION [patent_app_type] => utility [patent_app_number] => 17/128814 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128814 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128814
CONTEXT-BASED MEMORY INDIRECT BRANCH TARGET PREDICTION Dec 20, 2020 Abandoned
Array ( [id] => 16751435 [patent_doc_number] => 20210103444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => COMPUTER PROCESSOR FOR HIGHER PRECISION COMPUTATIONS USING A MIXED-PRECISION DECOMPOSITION OF OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/125846 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125846
Computer processor for higher precision computations using a mixed-precision decomposition of operations Dec 16, 2020 Issued
Array ( [id] => 18839388 [patent_doc_number] => 11847462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Software-based instruction scoreboard for arithmetic logic units [patent_app_type] => utility [patent_app_number] => 17/122089 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122089 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122089
Software-based instruction scoreboard for arithmetic logic units Dec 14, 2020 Issued
Array ( [id] => 17394759 [patent_doc_number] => 11243773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-08 [patent_title] => Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges [patent_app_type] => utility [patent_app_number] => 17/120371 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8936 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120371
Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges Dec 13, 2020 Issued
Array ( [id] => 16887461 [patent_doc_number] => 20210173658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => HIGH-LEVEL PROGRAMMING LANGUAGE WHICH UTILIZES VIRTUAL MEMORY [patent_app_type] => utility [patent_app_number] => 17/112072 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112072 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112072
High-level programming language which utilizes virtual memory Dec 3, 2020 Issued
Array ( [id] => 17528652 [patent_doc_number] => 11301340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Memory-based distributed processor architecture [patent_app_type] => utility [patent_app_number] => 17/112817 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 36303 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112817
Memory-based distributed processor architecture Dec 3, 2020 Issued
Array ( [id] => 16780123 [patent_doc_number] => 20210117202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHODS AND APPARATUS TO GENERATE GRAPHICS PROCESSING UNIT LONG INSTRUCTION TRACES [patent_app_type] => utility [patent_app_number] => 17/111136 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111136
Methods and apparatus to generate graphics processing unit long instruction traces Dec 2, 2020 Issued
Array ( [id] => 18711378 [patent_doc_number] => 20230334007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => DATA FLOW CONTROL DEVICE, DATA FLOW CONTROL METHOD, AND DATA FLOW CONTROL PROGRAM [patent_app_type] => utility [patent_app_number] => 18/035481 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18035481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/035481
Data flow control device, data flow control method, and data flow control program Nov 9, 2020 Issued
Array ( [id] => 17108211 [patent_doc_number] => 11128443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => SM3 hash algorithm acceleration processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 17/092133 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 18993 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092133
SM3 hash algorithm acceleration processors, methods, systems, and instructions Nov 5, 2020 Issued
Array ( [id] => 16690551 [patent_doc_number] => 20210073029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => SYNCHRONIZING SCHEDULING TASKS WITH ATOMIC ALU [patent_app_type] => utility [patent_app_number] => 17/087837 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087837 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087837
Synchronizing scheduling tasks with atomic ALU Nov 2, 2020 Issued
Array ( [id] => 19780045 [patent_doc_number] => 12229078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Neural processing unit synchronization systems and methods [patent_app_type] => utility [patent_app_number] => 18/006845 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15380 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18006845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/006845
Neural processing unit synchronization systems and methods Nov 1, 2020 Issued
Array ( [id] => 16887460 [patent_doc_number] => 20210173657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => Pipelines for Secure Multithread Execution [patent_app_type] => utility [patent_app_number] => 17/081074 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081074 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081074
Pipelines for secure multithread execution Oct 26, 2020 Issued
Array ( [id] => 17999534 [patent_doc_number] => 11500641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Devices, methods, and media for efficient data dependency management for in-order issue processors [patent_app_type] => utility [patent_app_number] => 17/065501 [patent_app_country] => US [patent_app_date] => 2020-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065501
Devices, methods, and media for efficient data dependency management for in-order issue processors Oct 6, 2020 Issued
Array ( [id] => 18015076 [patent_doc_number] => 11507372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Processing of instructions fetched from memory [patent_app_type] => utility [patent_app_number] => 17/064983 [patent_app_country] => US [patent_app_date] => 2020-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9549 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 492 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17064983 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/064983
Processing of instructions fetched from memory Oct 6, 2020 Issued
Array ( [id] => 19626091 [patent_doc_number] => 12164924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Compression metadata assisted computation [patent_app_type] => utility [patent_app_number] => 17/033308 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033308
Compression metadata assisted computation Sep 24, 2020 Issued
Array ( [id] => 16722163 [patent_doc_number] => 20210089310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => MULTIPROCESSOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/015642 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015642 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/015642
MULTIPROCESSOR DEVICE Sep 8, 2020 Abandoned
Array ( [id] => 17238280 [patent_doc_number] => 11182159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Vector reductions using shared scratchpad memory [patent_app_type] => utility [patent_app_number] => 17/007569 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13270 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007569
Vector reductions using shared scratchpad memory Aug 30, 2020 Issued
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