Thomas J. Mullen

Array ( [id] => 17744310 [patent_doc_number] => 11392377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => System-on-chip, data processing method thereof, and neural network device [patent_app_type] => utility [patent_app_number] => 17/007178 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7390 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17288215 [patent_doc_number] => 11204765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-21 [patent_title] => Deferred GPR allocation for texture/load instruction block [patent_app_type] => utility [patent_app_number] => 17/003600 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17572820 [patent_doc_number] => 11321088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Tracking load and store instructions and addresses in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 17/002378 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13770 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17415776 [patent_doc_number] => 20220050680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => TRACKING LOAD AND STORE INSTRUCTIONS AND ADDRESSES IN AN OUT-OF-ORDER PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/994070 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17401567 [patent_doc_number] => 20220043657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SYSTEM AND METHOD FOR CONVOLVING IMAGE WITH SPARSE KERNELS [patent_app_type] => utility [patent_app_number] => 16/987371 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16987371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16454625 [patent_doc_number] => 20200364051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => SYSTEM AND METHOD OF VLIW INSTRUCTION PROCESSING USING REDUCED-WIDTH VLIW PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/922885 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17338057 [patent_doc_number] => 20220004388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => COMMAND-AWARE HARDWARE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/921165 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17622029 [patent_doc_number] => 11341085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Low energy accelerator processor architecture with short parallel instruction word [patent_app_type] => utility [patent_app_number] => 16/920901 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 9858 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16393257 [patent_doc_number] => 20200334198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => VECTOR REDUCTION PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/918448 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16918448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17589480 [patent_doc_number] => 11327753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Processor instructions to accelerate FEC encoding and decoding [patent_app_type] => utility [patent_app_number] => 16/907715 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16907715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18119188 [patent_doc_number] => 11550582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Method and apparatus to process SHA-2 secure hashing algorithm [patent_app_type] => utility [patent_app_number] => 16/903542 [patent_app_country] => US [patent_app_date] => 2020-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 19547 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16577330 [patent_doc_number] => 20210011731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => PLC DEVICE [patent_app_type] => utility [patent_app_number] => 16/898936 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16898936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17294114 [patent_doc_number] => 20210389953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => Security Enhancement in Hierarchical Protection Domains [patent_app_type] => utility [patent_app_number] => 16/897959 [patent_app_country] => US [patent_app_date] => 2020-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16897959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17698897 [patent_doc_number] => 11372621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Circuitry for floating-point power function [patent_app_type] => utility [patent_app_number] => 16/893051 [patent_app_country] => US [patent_app_date] => 2020-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17260904 [patent_doc_number] => 20210373889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => PREFETCH MECHANISM FOR A CACHE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/887442 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16299881 [patent_doc_number] => 20200285604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS [patent_app_type] => utility [patent_app_number] => 16/884302 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17216387 [patent_doc_number] => 20210349725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => Multi-channel Data Path Circuitry [patent_app_type] => utility [patent_app_number] => 16/870330 [patent_app_country] => US [patent_app_date] => 2020-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16870330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17202060 [patent_doc_number] => 20210342155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => SYSTEM AND METHOD FOR PREFETCHING INSTRUCTIONS AND DATA [patent_app_type] => utility [patent_app_number] => 16/866202 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16508127 [patent_doc_number] => 20200387383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => SYSTEMS AND METHODS FOR IMPLEMENTING CHAINED TILE OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/863951 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17364912 [patent_doc_number] => 11231933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Processor with variable pre-fetch threshold [patent_app_type] => utility [patent_app_number] => 16/843998 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843998 [rel_patent_id] =>[rel_patent_doc_number] =>)