Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17157854 [patent_doc_number] => 20210318905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => OPERAND POOL INSTRUCTION RESERVATION CLUSTERING IN A SCHEDULER CIRCUIT IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/842898 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16842898 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/842898
Operand pool instruction reservation clustering in a scheduler circuit in a processor Apr 7, 2020 Issued
Array ( [id] => 19398938 [patent_doc_number] => 12073310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Deep neural network accelerator with independent datapaths for simultaneous processing of different classes of operations [patent_app_type] => utility [patent_app_number] => 16/837171 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/837171
Deep neural network accelerator with independent datapaths for simultaneous processing of different classes of operations Mar 31, 2020 Issued
Array ( [id] => 18136090 [patent_doc_number] => 11561767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Mixed-precision computation unit [patent_app_type] => utility [patent_app_number] => 16/836117 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 16390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836117 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836117
Mixed-precision computation unit Mar 30, 2020 Issued
Array ( [id] => 16178988 [patent_doc_number] => 20200225956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => OPERATION CACHE [patent_app_type] => utility [patent_app_number] => 16/834834 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834834 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834834
OPERATION CACHE Mar 29, 2020 Issued
Array ( [id] => 16346165 [patent_doc_number] => 20200310816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => PROCESSOR, DEVICE, AND METHOD FOR EXECUTING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/826146 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826146 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826146
Processor, device, and method for executing instructions Mar 19, 2020 Issued
Array ( [id] => 18606636 [patent_doc_number] => 11748100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Processing in memory methods for convolutional operations [patent_app_type] => utility [patent_app_number] => 16/824620 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14276 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824620 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/824620
Processing in memory methods for convolutional operations Mar 18, 2020 Issued
Array ( [id] => 17252837 [patent_doc_number] => 11188326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Function virtualization facility for function query of a processor [patent_app_type] => utility [patent_app_number] => 16/822560 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 20472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16822560 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/822560
Function virtualization facility for function query of a processor Mar 17, 2020 Issued
Array ( [id] => 17801955 [patent_doc_number] => 11416255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Instruction execution method and instruction execution device [patent_app_type] => utility [patent_app_number] => 16/813947 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6416 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813947 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/813947
Instruction execution method and instruction execution device Mar 9, 2020 Issued
Array ( [id] => 17054392 [patent_doc_number] => 20210263826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => DATA PROCESSING SYSTEM PERFORMANCE MONITORING [patent_app_type] => utility [patent_app_number] => 16/797530 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797530 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/797530
Data processing system performance monitoring Feb 20, 2020 Issued
Array ( [id] => 17636785 [patent_doc_number] => 11347509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Encoding and decoding variable length instructions [patent_app_type] => utility [patent_app_number] => 16/789366 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17138 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789366 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/789366
Encoding and decoding variable length instructions Feb 11, 2020 Issued
Array ( [id] => 16363172 [patent_doc_number] => 20200319923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => HIERARCHAL REGISTER FILE DEVICE BASED ON SPIN TRANSFER TORQUE-RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 16/782983 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782983 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/782983
Hierarchical register file device based on spin transfer torque-random access memory Feb 4, 2020 Issued
Array ( [id] => 18316909 [patent_doc_number] => 11630991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Broadcasting mode of planar engine for neural processor [patent_app_type] => utility [patent_app_number] => 16/781824 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 15063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/781824
Broadcasting mode of planar engine for neural processor Feb 3, 2020 Issued
Array ( [id] => 16864490 [patent_doc_number] => 11023230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Apparatus for calculating and retaining a bound on error during floating-point operations and methods thereof [patent_app_type] => utility [patent_app_number] => 16/747477 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17689 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747477
Apparatus for calculating and retaining a bound on error during floating-point operations and methods thereof Jan 19, 2020 Issued
Array ( [id] => 16192815 [patent_doc_number] => 20200233664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => EFFICIENT RANGE-BASED MEMORY WRITEBACK TO IMPROVE HOST TO DEVICE COMMUNICATION FOR OPTIMAL POWER AND PERFORMANCE [patent_app_type] => utility [patent_app_number] => 16/717258 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717258 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717258
EFFICIENT RANGE-BASED MEMORY WRITEBACK TO IMPROVE HOST TO DEVICE COMMUNICATION FOR OPTIMAL POWER AND PERFORMANCE Dec 16, 2019 Abandoned
Array ( [id] => 18015074 [patent_doc_number] => 11507370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Method and device for dynamically adjusting decimal point positions in neural network computations [patent_app_type] => utility [patent_app_number] => 16/715062 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 27694 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715062
Method and device for dynamically adjusting decimal point positions in neural network computations Dec 15, 2019 Issued
Array ( [id] => 17252845 [patent_doc_number] => 11188334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions [patent_app_type] => utility [patent_app_number] => 16/699808 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 12272 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699808
Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions Dec 1, 2019 Issued
Array ( [id] => 18087721 [patent_doc_number] => 11537858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Computing device and method [patent_app_type] => utility [patent_app_number] => 16/698988 [patent_app_country] => US [patent_app_date] => 2019-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 6711 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698988 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/698988
Computing device and method Nov 27, 2019 Issued
Array ( [id] => 15715891 [patent_doc_number] => 20200104713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => COMPUTING DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/698979 [patent_app_country] => US [patent_app_date] => 2019-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698979 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/698979
Sparse training in neural networks Nov 27, 2019 Issued
Array ( [id] => 15744199 [patent_doc_number] => 20200110988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => COMPUTING DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/698976 [patent_app_country] => US [patent_app_date] => 2019-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/698976
Computing device and method Nov 27, 2019 Issued
Array ( [id] => 16856843 [patent_doc_number] => 20210157588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => DEDICATED VECTOR SUB-PROCESSOR SYSTEM [patent_app_type] => utility [patent_app_number] => 16/697660 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697660 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697660
Dedicated vector sub-processor system Nov 26, 2019 Issued
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