Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16690522 [patent_doc_number] => 20210073000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => REUSING ADJACENT SIMD UNIT FOR FAST WIDE RESULT GENERATION [patent_app_type] => utility [patent_app_number] => 16/565946 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16565946 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/565946
Reusing adjacent SIMD unit for fast wide result generation Sep 9, 2019 Issued
Array ( [id] => 15328419 [patent_doc_number] => 20200004539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => CODE-SPECIFIC AFFILIATED REGISTER PREDICTION [patent_app_type] => utility [patent_app_number] => 16/562906 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562906 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/562906
Code-specific affiliated register prediction Sep 5, 2019 Issued
Array ( [id] => 15328429 [patent_doc_number] => 20200004544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => DETERMINING AND PREDICTING DERIVED VALUES [patent_app_type] => utility [patent_app_number] => 16/562959 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562959 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/562959
Determining and predicting derived values Sep 5, 2019 Issued
Array ( [id] => 16584777 [patent_doc_number] => 20210019179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => K-TIER ARCHITECTURE SCHEDULING [patent_app_type] => utility [patent_app_number] => 16/516513 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516513 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516513
K-tier architecture scheduling Jul 18, 2019 Issued
Array ( [id] => 17143729 [patent_doc_number] => 20210311742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => AN APPARATUS AND METHOD FOR PREDICTING SOURCE OPERAND VALUES AND OPTIMIZED PROCESSING OF INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/266759 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17266759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/266759
Apparatus and method for predicting source operand values and optimized processing of instructions Jul 16, 2019 Issued
Array ( [id] => 16818628 [patent_doc_number] => 11003454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Apparatus and method for speculative execution of instructions [patent_app_type] => utility [patent_app_number] => 16/514124 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8092 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514124 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514124
Apparatus and method for speculative execution of instructions Jul 16, 2019 Issued
Array ( [id] => 17106294 [patent_doc_number] => 11126511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Memory-based distributed processor architecture [patent_app_type] => utility [patent_app_number] => 16/512622 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 36285 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512622 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512622
Memory-based distributed processor architecture Jul 15, 2019 Issued
Array ( [id] => 15090339 [patent_doc_number] => 20190339980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => MEMORY-BASED DISTRIBUTED PROCESSOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/512562 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512562 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512562
Memory-based distributed processor architecture Jul 15, 2019 Issued
Array ( [id] => 15500535 [patent_doc_number] => 20200050456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => Method for Processing Information, and Processor [patent_app_type] => utility [patent_app_number] => 16/502628 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502628
Processor, and method for processing information applied to processor Jul 2, 2019 Issued
Array ( [id] => 16879803 [patent_doc_number] => 11029950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Reducing latency of common source data movement instructions [patent_app_type] => utility [patent_app_number] => 16/502231 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502231 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502231
Reducing latency of common source data movement instructions Jul 2, 2019 Issued
Array ( [id] => 16543298 [patent_doc_number] => 20200409713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => CORE-TO-CORE END "OFFLOAD" INSTRUCTION(S) [patent_app_type] => utility [patent_app_number] => 16/457970 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457970 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457970
Core-to-core end "offload" instruction(s) Jun 28, 2019 Issued
Array ( [id] => 17771156 [patent_doc_number] => 11403097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Systems and methods to skip inconsequential matrix operations [patent_app_type] => utility [patent_app_number] => 16/453724 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 51 [patent_no_of_words] => 27245 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453724 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453724
Systems and methods to skip inconsequential matrix operations Jun 25, 2019 Issued
Array ( [id] => 16200616 [patent_doc_number] => 10725779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Method and apparatus to process SHA-2 secure hashing algorithm [patent_app_type] => utility [patent_app_number] => 16/450319 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 19536 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450319 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/450319
Method and apparatus to process SHA-2 secure hashing algorithm Jun 23, 2019 Issued
Array ( [id] => 15328431 [patent_doc_number] => 20200004545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => INFORMATION PROCESSING DEVICE AND NON-TRANSITORY COMPUTER READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/442567 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16442567 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/442567
INFORMATION PROCESSING DEVICE AND NON-TRANSITORY COMPUTER READABLE MEDIUM Jun 16, 2019 Abandoned
Array ( [id] => 16454630 [patent_doc_number] => 20200364056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => FACILITATING DATA PROCESSING USING SIMD REDUCTION OPERATIONS ACROSS SIMD LANES [patent_app_type] => utility [patent_app_number] => 16/412072 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412072 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412072
Facilitating data processing using SIMD reduction operations across SIMD lanes May 13, 2019 Issued
Array ( [id] => 16431416 [patent_doc_number] => 10831498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Managing an issue queue for fused instructions and paired instructions in a microprocessor [patent_app_type] => utility [patent_app_number] => 16/409993 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7265 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16409993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/409993
Managing an issue queue for fused instructions and paired instructions in a microprocessor May 12, 2019 Issued
Array ( [id] => 17252843 [patent_doc_number] => 11188332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => System and handling of register data in processors [patent_app_type] => utility [patent_app_number] => 16/408687 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10471 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408687 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/408687
System and handling of register data in processors May 9, 2019 Issued
Array ( [id] => 16706226 [patent_doc_number] => 10956158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => System and handling of register data in processors [patent_app_type] => utility [patent_app_number] => 16/408749 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11187 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/408749
System and handling of register data in processors May 9, 2019 Issued
Array ( [id] => 17202057 [patent_doc_number] => 20210342152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => HANDLING LOAD-EXCLUSIVE INSTRUCTIONS IN APPARATUS HAVING SUPPORT FOR TRANSACTIONAL MEMORY [patent_app_type] => utility [patent_app_number] => 17/255001 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17255001 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/255001
Handling load-exclusive instructions in apparatus having support for transactional memory May 8, 2019 Issued
Array ( [id] => 15090417 [patent_doc_number] => 20190340019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Thread Commencement and Completion Using Work Descriptor Packets in a System Having a Self-Scheduling Processor and a Hybrid Threading Fabric [patent_app_type] => utility [patent_app_number] => 16/399642 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399642 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399642
Thread commencement and completion using work descriptor packets in a system having a self-scheduling processor and a hybrid threading fabric Apr 29, 2019 Issued
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