Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13432525 [patent_doc_number] => 20180267805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => HANDLING STALLING EVENT FOR MULTIPLE THREAD PIPELINE, AND TRIGGERING ACTION BASED ON INFORMATION ACCESS DELAY [patent_app_type] => utility [patent_app_number] => 15/987113 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987113
Handling stalling event for multiple thread pipeline, and triggering action based on information access delay May 22, 2018 Issued
Array ( [id] => 13830675 [patent_doc_number] => 20190018822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => Method and Apparatus for Constructing Multivalued Microprocessor [patent_app_type] => utility [patent_app_number] => 15/984518 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15984518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/984518
Method and apparatus for constructing multivalued microprocessor May 20, 2018 Issued
Array ( [id] => 15151783 [patent_doc_number] => 20190354369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => COMPUTING ARCHITECTURE TO PROVIDE SIMPLIFIED POST-SILICON DEBUGGING CAPABILITIES [patent_app_type] => utility [patent_app_number] => 15/979627 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/979627
COMPUTING ARCHITECTURE TO PROVIDE SIMPLIFIED POST-SILICON DEBUGGING CAPABILITIES May 14, 2018 Abandoned
Array ( [id] => 13568961 [patent_doc_number] => 20180336028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => PROCESSING DEVICE AND CONTROL METHOD OF PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 15/980115 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/980115
PROCESSING DEVICE AND CONTROL METHOD OF PROCESSING DEVICE May 14, 2018 Abandoned
Array ( [id] => 15151787 [patent_doc_number] => 20190354371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => DENTIFYING AND TRACKING FREQUENTLY ACCESSED REGISTERS IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/979657 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979657 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/979657
Identifying and tracking frequently accessed registers in a processor May 14, 2018 Issued
Array ( [id] => 16651950 [patent_doc_number] => 10929127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Systems, methods, and apparatuses utilizing an elastic floating-point number [patent_app_type] => utility [patent_app_number] => 15/973816 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 16771 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15973816 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/973816
Systems, methods, and apparatuses utilizing an elastic floating-point number May 7, 2018 Issued
Array ( [id] => 17636784 [patent_doc_number] => 11347508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Apparatus and method for managing a capability domain [patent_app_type] => utility [patent_app_number] => 16/607462 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10113 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16607462 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/607462
Apparatus and method for managing a capability domain Apr 26, 2018 Issued
Array ( [id] => 15670415 [patent_doc_number] => 10599437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Managing obscured branch prediction information [patent_app_type] => utility [patent_app_number] => 15/963243 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9005 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15963243 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/963243
Managing obscured branch prediction information Apr 25, 2018 Issued
Array ( [id] => 15805583 [patent_doc_number] => 20200125934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => MICROTHREADING FOR ACCELERATED DEEP LEARNING [patent_app_type] => utility [patent_app_number] => 16/603950 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 62463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -41 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603950 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603950
Microthreading for accelerated deep learning Apr 16, 2018 Issued
Array ( [id] => 13497191 [patent_doc_number] => 20180300138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => HUMAN-MACHINE-INTERFACE SYSTEM [patent_app_type] => utility [patent_app_number] => 15/943926 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943926 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943926
Human-machine-interface system comprising a convolutional neural network hardware accelerator Apr 2, 2018 Issued
Array ( [id] => 15788871 [patent_doc_number] => 10628160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Selective poisoning of data during runahead [patent_app_type] => utility [patent_app_number] => 15/943509 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6795 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943509 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943509
Selective poisoning of data during runahead Apr 1, 2018 Issued
Array ( [id] => 16248182 [patent_doc_number] => 10747541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Managing predictor selection for branch prediction [patent_app_type] => utility [patent_app_number] => 15/880219 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8559 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880219
Managing predictor selection for branch prediction Jan 24, 2018 Issued
Array ( [id] => 15399049 [patent_doc_number] => 10540181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Managing branch prediction information for different contexts [patent_app_type] => utility [patent_app_number] => 15/880188 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8745 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880188 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880188
Managing branch prediction information for different contexts Jan 24, 2018 Issued
Array ( [id] => 13332615 [patent_doc_number] => 20180217845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => CODE GENERATION APPARATUS AND CODE GENERATION METHOD [patent_app_type] => utility [patent_app_number] => 15/878781 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15878781 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/878781
CODE GENERATION APPARATUS AND CODE GENERATION METHOD Jan 23, 2018 Abandoned
Array ( [id] => 14539019 [patent_doc_number] => 20190205131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR VECTOR BROADCAST [patent_app_type] => utility [patent_app_number] => 15/858278 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858278 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858278
SYSTEMS, METHODS, AND APPARATUSES FOR VECTOR BROADCAST Dec 28, 2017 Abandoned
Array ( [id] => 13906061 [patent_doc_number] => 20190042235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => SYSTEMS AND METHODS FOR COMPUTING DOT PRODUCTS OF NIBBLES IN TWO TILE OPERANDS [patent_app_type] => utility [patent_app_number] => 15/858916 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858916 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858916
Systems and methods for computing dot products of nibbles in two tile operands Dec 28, 2017 Issued
Array ( [id] => 15854675 [patent_doc_number] => 10642621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => System, apparatus and method for controlling allocations into a branch prediction circuit of a processor [patent_app_type] => utility [patent_app_number] => 15/857863 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9434 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857863
System, apparatus and method for controlling allocations into a branch prediction circuit of a processor Dec 28, 2017 Issued
Array ( [id] => 12688375 [patent_doc_number] => 20180121291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => Simultaneous Multi-Processor Apparatus Applicable to Acheiving Exascale Performance for Algorithms and Program Systems [patent_app_type] => utility [patent_app_number] => 15/844740 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844740 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844740
Simultaneous multi-processor apparatus applicable to achieving exascale performance for algorithms and program systems Dec 17, 2017 Issued
Array ( [id] => 14443539 [patent_doc_number] => 20190179643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => DIFFERENTIAL PIPLINE DELAYS IN A COPROCESSOR [patent_app_type] => utility [patent_app_number] => 15/837974 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837974 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837974
Differential pipeline delays in a coprocessor Dec 10, 2017 Issued
Array ( [id] => 12646971 [patent_doc_number] => 20180107488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION [patent_app_type] => utility [patent_app_number] => 15/836133 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29836 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836133 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/836133
Restricted instructions in transactional execution Dec 7, 2017 Issued
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