
Thomas J. Mullen
Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )
| Most Active Art Unit | 2685 |
| Art Unit(s) | 2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608 |
| Total Applications | 2648 |
| Issued Applications | 2205 |
| Pending Applications | 106 |
| Abandoned Applications | 342 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12628668
[patent_doc_number] => 20180101386
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-12
[patent_title] => RESTRICTED INSTRUCTIONS IN TRANSACTIONAL EXECUTION
[patent_app_type] => utility
[patent_app_number] => 15/836019
[patent_app_country] => US
[patent_app_date] => 2017-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29822
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836019
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/836019 | Restricted instructions in transactional execution | Dec 7, 2017 | Issued |
Array
(
[id] => 15952723
[patent_doc_number] => 10664269
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-26
[patent_title] => Function virtualization facility for function query of a processor
[patent_app_type] => utility
[patent_app_number] => 15/835576
[patent_app_country] => US
[patent_app_date] => 2017-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 25
[patent_no_of_words] => 20586
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 372
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835576
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/835576 | Function virtualization facility for function query of a processor | Dec 7, 2017 | Issued |
Array
(
[id] => 14872415
[patent_doc_number] => 20190286449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-19
[patent_title] => SYSTEM AND METHOD FOR AUTOMATED AGGREGATION OF SYSTEM INFORMATION FROM DISPARATE INFORMATION SOURCES
[patent_app_type] => utility
[patent_app_number] => 16/464054
[patent_app_country] => US
[patent_app_date] => 2017-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9838
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16464054
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/464054 | SYSTEM AND METHOD FOR AUTOMATED AGGREGATION OF SYSTEM INFORMATION FROM DISPARATE INFORMATION SOURCES | Nov 27, 2017 | Abandoned |
Array
(
[id] => 13961215
[patent_doc_number] => 20190056952
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-21
[patent_title] => PREDICTION OF AN AFFILIATED REGISTER
[patent_app_type] => utility
[patent_app_number] => 15/822866
[patent_app_country] => US
[patent_app_date] => 2017-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19220
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822866
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/822866 | Prediction of an affiliated register | Nov 26, 2017 | Issued |
Array
(
[id] => 12611814
[patent_doc_number] => 20180095768
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-05
[patent_title] => CLOCK-GATING FOR MULTICYCLE INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 15/822261
[patent_app_country] => US
[patent_app_date] => 2017-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9388
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822261
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/822261 | Clock-gating for multicycle instructions | Nov 26, 2017 | Issued |
Array
(
[id] => 12755995
[patent_doc_number] => 20180143832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-24
[patent_title] => Encoding and Decoding Variable Length Instructions
[patent_app_type] => utility
[patent_app_number] => 15/821930
[patent_app_country] => US
[patent_app_date] => 2017-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17093
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15821930
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/821930 | Encoding and decoding variable length instructions | Nov 23, 2017 | Issued |
Array
(
[id] => 12755998
[patent_doc_number] => 20180143833
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-24
[patent_title] => METHOD AND SYSTEM FOR MANAGING CONTROL OF INSTRUCTION AND PROCESS EXECUTION IN A PROGRAMMABLE COMPUTING SYSTEM
[patent_app_type] => utility
[patent_app_number] => 15/820264
[patent_app_country] => US
[patent_app_date] => 2017-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9663
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820264
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/820264 | Method and system for managing control of instruction and process execution in a programmable computing system | Nov 20, 2017 | Issued |
Array
(
[id] => 15486223
[patent_doc_number] => 10558461
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-11
[patent_title] => Determining and predicting derived values used in register-indirect branching
[patent_app_type] => utility
[patent_app_number] => 15/819450
[patent_app_country] => US
[patent_app_date] => 2017-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 19185
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819450
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/819450 | Determining and predicting derived values used in register-indirect branching | Nov 20, 2017 | Issued |
Array
(
[id] => 15516777
[patent_doc_number] => 10564974
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-18
[patent_title] => Determining and predicting affiliated registers based on dynamic runtime control flow analysis
[patent_app_type] => utility
[patent_app_number] => 15/819524
[patent_app_country] => US
[patent_app_date] => 2017-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 19242
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819524
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/819524 | Determining and predicting affiliated registers based on dynamic runtime control flow analysis | Nov 20, 2017 | Issued |
Array
(
[id] => 15398973
[patent_doc_number] => 10540143
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-21
[patent_title] => Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof
[patent_app_type] => utility
[patent_app_number] => 15/811617
[patent_app_country] => US
[patent_app_date] => 2017-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 17314
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 289
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811617
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/811617 | Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof | Nov 12, 2017 | Issued |
Array
(
[id] => 13738141
[patent_doc_number] => 20180373539
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-27
[patent_title] => SYSTEM AND METHOD OF MERGING PARTIAL WRITE RESULTS FOR RESOLVING RENAMING SIZE ISSUES
[patent_app_type] => utility
[patent_app_number] => 15/810876
[patent_app_country] => US
[patent_app_date] => 2017-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5943
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810876
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/810876 | System and method of merging partial write results for resolving renaming size issues | Nov 12, 2017 | Issued |
Array
(
[id] => 14282053
[patent_doc_number] => 20190138311
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => SYSTEM AND METHOD OF VLIW INSTRUCTION PROCESSING USING REDUCED-WIDTH VLIW PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 15/805935
[patent_app_country] => US
[patent_app_date] => 2017-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8188
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15805935
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/805935 | System and method of VLIW instruction processing using reduced-width VLIW processor | Nov 6, 2017 | Issued |
Array
(
[id] => 16574461
[patent_doc_number] => 10896386
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-19
[patent_title] => Computerized branch predictions and decisions
[patent_app_type] => utility
[patent_app_number] => 15/802776
[patent_app_country] => US
[patent_app_date] => 2017-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6846
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802776
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/802776 | Computerized branch predictions and decisions | Nov 2, 2017 | Issued |
Array
(
[id] => 15982143
[patent_doc_number] => 10671399
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core
[patent_app_type] => utility
[patent_app_number] => 15/796032
[patent_app_country] => US
[patent_app_date] => 2017-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3934
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796032
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/796032 | Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core | Oct 26, 2017 | Issued |
Array
(
[id] => 16270990
[patent_doc_number] => 20200272478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-27
[patent_title] => VECTOR PROCESSOR AND CONTROL METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 16/462086
[patent_app_country] => US
[patent_app_date] => 2017-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16462086
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/462086 | Vector processor and control method therefor | Oct 22, 2017 | Issued |
Array
(
[id] => 16232729
[patent_doc_number] => 10740280
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-11
[patent_title] => Low energy accelerator processor architecture with short parallel instruction word
[patent_app_type] => utility
[patent_app_number] => 15/714212
[patent_app_country] => US
[patent_app_date] => 2017-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 9837
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714212
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/714212 | Low energy accelerator processor architecture with short parallel instruction word | Sep 24, 2017 | Issued |
Array
(
[id] => 15074947
[patent_doc_number] => 10466964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-05
[patent_title] => Engine architecture for processing finite automata
[patent_app_type] => utility
[patent_app_number] => 15/703638
[patent_app_country] => US
[patent_app_date] => 2017-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 33
[patent_no_of_words] => 33060
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703638
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/703638 | Engine architecture for processing finite automata | Sep 12, 2017 | Issued |
Array
(
[id] => 16065011
[patent_doc_number] => 10691455
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-23
[patent_title] => Power saving branch modes in hardware
[patent_app_type] => utility
[patent_app_number] => 15/684573
[patent_app_country] => US
[patent_app_date] => 2017-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 6840
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15684573
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/684573 | Power saving branch modes in hardware | Aug 22, 2017 | Issued |
Array
(
[id] => 15386849
[patent_doc_number] => 10534609
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-14
[patent_title] => Code-specific affiliated register prediction
[patent_app_type] => utility
[patent_app_number] => 15/680881
[patent_app_country] => US
[patent_app_date] => 2017-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 19271
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680881
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/680881 | Code-specific affiliated register prediction | Aug 17, 2017 | Issued |
Array
(
[id] => 16185996
[patent_doc_number] => 10719328
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-21
[patent_title] => Determining and predicting derived values used in register-indirect branching
[patent_app_type] => utility
[patent_app_number] => 15/680855
[patent_app_country] => US
[patent_app_date] => 2017-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 19217
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680855
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/680855 | Determining and predicting derived values used in register-indirect branching | Aug 17, 2017 | Issued |