Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16551587 [patent_doc_number] => 10884746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Determining and predicting affiliated registers based on dynamic runtime control flow analysis [patent_app_type] => utility [patent_app_number] => 15/680824 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 19213 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680824 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/680824
Determining and predicting affiliated registers based on dynamic runtime control flow analysis Aug 17, 2017 Issued
Array ( [id] => 16551588 [patent_doc_number] => 10884747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Prediction of an affiliated register [patent_app_type] => utility [patent_app_number] => 15/680871 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 19201 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680871 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/680871
Prediction of an affiliated register Aug 17, 2017 Issued
Array ( [id] => 17469106 [patent_doc_number] => 11275583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Apparatus and method of improved insert instructions [patent_app_type] => utility [patent_app_number] => 15/668461 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 43 [patent_no_of_words] => 21965 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15668461 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/668461
Apparatus and method of improved insert instructions Aug 2, 2017 Issued
Array ( [id] => 15982141 [patent_doc_number] => 10671398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core [patent_app_type] => utility [patent_app_number] => 15/666822 [patent_app_country] => US [patent_app_date] => 2017-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3934 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15666822 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/666822
Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core Aug 1, 2017 Issued
Array ( [id] => 15935801 [patent_doc_number] => 20200159534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => SYSTEM AND METHOD ENABLING ONE-HOT NEURAL NETWORKS ON A MACHINE LEARNING COMPUTE PLATFORM [patent_app_type] => utility [patent_app_number] => 16/633071 [patent_app_country] => US [patent_app_date] => 2017-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16633071 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/633071
System and method enabling one-hot neural networks on a machine learning compute platform Aug 1, 2017 Issued
Array ( [id] => 16346236 [patent_doc_number] => 20200310887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD FOR SYNCHRONIZED OPERATION OF MULTICORE PROCESSORS [patent_app_type] => utility [patent_app_number] => 16/311970 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16311970 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/311970
Method for synchronized operation of multicore processors May 31, 2017 Issued
Array ( [id] => 13579879 [patent_doc_number] => 20180341488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => MICROPROCESSOR INSTRUCTION PREDISPATCH BEFORE BLOCK COMMIT [patent_app_type] => utility [patent_app_number] => 15/606673 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606673 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/606673
MICROPROCESSOR INSTRUCTION PREDISPATCH BEFORE BLOCK COMMIT May 25, 2017 Abandoned
Array ( [id] => 13721401 [patent_doc_number] => 20170371655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => PROCESSOR AND CONTROL METHOD OF PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/606097 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606097 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/606097
PROCESSOR AND CONTROL METHOD OF PROCESSOR May 25, 2017 Abandoned
Array ( [id] => 13569887 [patent_doc_number] => 20180336491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => COMPUTERIZED BRANCH PREDICTIONS AND DECISIONS [patent_app_type] => utility [patent_app_number] => 15/599770 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599770 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599770
Computerized branch predictions and decisions May 18, 2017 Issued
Array ( [id] => 13525969 [patent_doc_number] => 20180314527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => PROCESSING OPERATION ISSUE CONTROL [patent_app_type] => utility [patent_app_number] => 15/497461 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497461 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/497461
Processing operation issue control Apr 25, 2017 Issued
Array ( [id] => 12032806 [patent_doc_number] => 20170322905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'APPARATUS AND METHOD OF MASK PERMUTE INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 15/495933 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16468 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15495933 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/495933
Apparatus and method of mask permute instructions Apr 23, 2017 Issued
Array ( [id] => 13511897 [patent_doc_number] => 20180307491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => EARLY PREDICATE LOOK-UP [patent_app_type] => utility [patent_app_number] => 15/493492 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493492 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493492
Early predicate look-up Apr 20, 2017 Issued
Array ( [id] => 15106289 [patent_doc_number] => 10474469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Apparatus and method for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow [patent_app_type] => utility [patent_app_number] => 15/485507 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 13785 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/485507
Apparatus and method for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow Apr 11, 2017 Issued
Array ( [id] => 13483067 [patent_doc_number] => 20180293076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => BRANCH PREDICTOR SELECTION MANAGEMENT [patent_app_type] => utility [patent_app_number] => 15/479326 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479326 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/479326
Branch predictor selection management Apr 4, 2017 Issued
Array ( [id] => 13467137 [patent_doc_number] => 20180285111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => METHOD OF DETECTING REPETITION OF AN OUT-OF-ORDER EXECUTION SCHEDULE, APPARATUS AND COMPUTER-READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 15/478552 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478552 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/478552
Method of detecting repetition of an out-of-order execution schedule, apparatus and computer-readable medium Apr 3, 2017 Issued
Array ( [id] => 11996167 [patent_doc_number] => 20170300322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'ARITHMETIC PROCESSING DEVICE, METHOD, AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/478528 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5782 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478528 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/478528
ARITHMETIC PROCESSING DEVICE, METHOD, AND SYSTEM Apr 3, 2017 Abandoned
Array ( [id] => 13186121 [patent_doc_number] => 10108581 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-23 [patent_title] => Vector reduction processor [patent_app_type] => utility [patent_app_number] => 15/477791 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14561 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477791
Vector reduction processor Apr 2, 2017 Issued
Array ( [id] => 13467145 [patent_doc_number] => 20180285115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => MISPREDICTION-TRIGGERED LOCAL HISTORY-BASED BRANCH PREDICTION [patent_app_type] => utility [patent_app_number] => 15/477064 [patent_app_country] => US [patent_app_date] => 2017-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477064 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477064
Misprediction-triggered local history-based branch prediction Mar 31, 2017 Issued
Array ( [id] => 13467125 [patent_doc_number] => 20180285105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => EFFICIENT RANGE-BASED MEMORY WRITEBACK TO IMPROVE HOST TO DEVICE COMMMUNICATION FOR OPTIMAL POWER AND PERFORMANCE [patent_app_type] => utility [patent_app_number] => 15/476302 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476302 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/476302
Efficient range-based memory writeback to improve host to device communication for optimal power and performance Mar 30, 2017 Issued
Array ( [id] => 15399041 [patent_doc_number] => 10540177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Efficient zero-based decompression [patent_app_type] => utility [patent_app_number] => 15/438712 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 16050 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438712 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/438712
Efficient zero-based decompression Feb 20, 2017 Issued
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