Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14330637 [patent_doc_number] => 10296337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Preventing premature reads from a general purpose register [patent_app_type] => utility [patent_app_number] => 15/075771 [patent_app_country] => US [patent_app_date] => 2016-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8137 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15075771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/075771
Preventing premature reads from a general purpose register Mar 20, 2016 Issued
Array ( [id] => 11516261 [patent_doc_number] => 20170083335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'BROADCAST CHANNEL ARCHITECTURES FOR BLOCK-BASED PROCESSORS' [patent_app_type] => utility [patent_app_number] => 15/074938 [patent_app_country] => US [patent_app_date] => 2016-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 20158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15074938 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/074938
Broadcast channel architectures for block-based processors Mar 17, 2016 Issued
Array ( [id] => 11516247 [patent_doc_number] => 20170083322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'MULTIMODAL TARGETS IN A BLOCK-BASED PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/073365 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073365
Multimodal targets in a block-based processor Mar 16, 2016 Issued
Array ( [id] => 13767291 [patent_doc_number] => 10175987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Instruction prefetching in a computer processor using a prefetch prediction vector [patent_app_type] => utility [patent_app_number] => 15/072717 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6282 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072717 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/072717
Instruction prefetching in a computer processor using a prefetch prediction vector Mar 16, 2016 Issued
Array ( [id] => 11516257 [patent_doc_number] => 20170083331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'MEMORY SYNCHRONIZATION IN BLOCK-BASED PROCESSORS' [patent_app_type] => utility [patent_app_number] => 15/072031 [patent_app_country] => US [patent_app_date] => 2016-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072031 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/072031
MEMORY SYNCHRONIZATION IN BLOCK-BASED PROCESSORS Mar 15, 2016 Abandoned
Array ( [id] => 11226654 [patent_doc_number] => 09454377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Speculative branch handling for transaction abort' [patent_app_type] => utility [patent_app_number] => 15/052090 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3707 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052090 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052090
Speculative branch handling for transaction abort Feb 23, 2016 Issued
Array ( [id] => 11838620 [patent_doc_number] => 20170220341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'STOCHASTIC ROUNDING FLOATING-POINT MULTIPLY INSTRUCTION USING ENTROPY FROM A REGISTER' [patent_app_type] => utility [patent_app_number] => 15/009372 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7059 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009372 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/009372
Stochastic rounding floating-point multiply instruction using entropy from a register Jan 27, 2016 Issued
Array ( [id] => 11838622 [patent_doc_number] => 20170220342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'STOCHASTIC ROUNDING FLOATING-POINT ADD INSTRUCTION USING ENTROPY FROM A REGISTER' [patent_app_type] => utility [patent_app_number] => 15/009397 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7452 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009397 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/009397
Stochastic rounding floating-point add instruction using entropy from a register Jan 27, 2016 Issued
Array ( [id] => 11745667 [patent_doc_number] => 20170199741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'INSTRUCTION TRANSFER CONTROL USING PROGRAM COUNTERS' [patent_app_type] => utility [patent_app_number] => 14/994796 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994796 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/994796
Processing instruction control transfer instructions Jan 12, 2016 Issued
Array ( [id] => 13919673 [patent_doc_number] => 10203959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-12 [patent_title] => Subroutine power optimiztion [patent_app_type] => utility [patent_app_number] => 14/993627 [patent_app_country] => US [patent_app_date] => 2016-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6341 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14993627 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/993627
Subroutine power optimiztion Jan 11, 2016 Issued
Array ( [id] => 12120945 [patent_doc_number] => 20180004530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'ADVANCED PROCESSOR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/535697 [patent_app_country] => US [patent_app_date] => 2015-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 31410 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15535697 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/535697
Advanced processor architecture Dec 12, 2015 Issued
Array ( [id] => 11245270 [patent_doc_number] => 09471313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-18 [patent_title] => 'Flushing speculative instruction processing' [patent_app_type] => utility [patent_app_number] => 14/952020 [patent_app_country] => US [patent_app_date] => 2015-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17196 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/952020
Flushing speculative instruction processing Nov 24, 2015 Issued
Array ( [id] => 13226541 [patent_doc_number] => 10127046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Mechanism to preclude uncacheable-dependent load replays in out-of-order processor [patent_app_type] => utility [patent_app_number] => 14/950331 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10258 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950331 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950331
Mechanism to preclude uncacheable-dependent load replays in out-of-order processor Nov 23, 2015 Issued
Array ( [id] => 10824594 [patent_doc_number] => 20160170760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'APPARATUS AND METHOD TO PRECLUDE NON-CORE CACHE-DEPENDENT LOAD REPLAYS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/950582 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10807 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950582 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950582
Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor Nov 23, 2015 Issued
Array ( [id] => 13268909 [patent_doc_number] => 10146539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Load replay precluding mechanism [patent_app_type] => utility [patent_app_number] => 14/950365 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10235 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950365 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950365
Load replay precluding mechanism Nov 23, 2015 Issued
Array ( [id] => 10824597 [patent_doc_number] => 20160170763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'APPARATUS AND METHOD TO PRECLUDE LOAD REPLAYS DEPENDENT ON WRITE COMBINING MEMORY SPACE ACCESS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/950684 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10787 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950684 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950684
Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor Nov 23, 2015 Issued
Array ( [id] => 10824590 [patent_doc_number] => 20160170756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON LONG LOAD CYCLES IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/950415 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10747 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950415 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950415
Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor Nov 23, 2015 Issued
Array ( [id] => 10824595 [patent_doc_number] => 20160170761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON OFF-DIE CONTROL ELEMENT ACCESS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/950615 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10727 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950615 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950615
Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor Nov 23, 2015 Issued
Array ( [id] => 10824598 [patent_doc_number] => 20160170764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'APPARATUS AND METHOD FOR PROGRAMMABLE LOAD REPLAY PRECLUSION' [patent_app_type] => utility [patent_app_number] => 14/950713 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10838 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950713 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950713
Apparatus and method for programmable load replay preclusion Nov 23, 2015 Issued
Array ( [id] => 13143101 [patent_doc_number] => 10088881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Mechanism to preclude I/O-dependent load replays in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 14/950306 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10257 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950306 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950306
Mechanism to preclude I/O-dependent load replays in an out-of-order processor Nov 23, 2015 Issued
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