Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10824591 [patent_doc_number] => 20160170757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'PROGRAMMABLE LOAD REPLAY PRECLUDING MECHANISM' [patent_app_type] => utility [patent_app_number] => 14/950439 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10786 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950439 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950439
Programmable load replay precluding mechanism Nov 23, 2015 Issued
Array ( [id] => 10824593 [patent_doc_number] => 20160170759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'MECHANISM TO PRECLUDE SHARED RAM-DEPENDENT LOAD REPLAYS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/950555 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10799 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950555 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950555
Mechanism to preclude shared ram-dependent load replays in an out-of-order processor Nov 23, 2015 Issued
Array ( [id] => 13143557 [patent_doc_number] => 10089112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 14/950283 [patent_app_country] => US [patent_app_date] => 2015-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10309 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950283 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/950283
Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor Nov 23, 2015 Issued
Array ( [id] => 11516267 [patent_doc_number] => 20170083341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'SEGMENTED INSTRUCTION BLOCK' [patent_app_type] => utility [patent_app_number] => 14/942345 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 22716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942345 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942345
SEGMENTED INSTRUCTION BLOCK Nov 15, 2015 Abandoned
Array ( [id] => 11516358 [patent_doc_number] => 20170083431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'DEBUG SUPPORT FOR BLOCK-BASED PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/942557 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 22512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942557 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942557
Debug support for block-based processor Nov 15, 2015 Issued
Array ( [id] => 16278821 [patent_doc_number] => 10761852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Extending data range addressing [patent_app_type] => utility [patent_app_number] => 14/871959 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 11378 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871959 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/871959
Extending data range addressing Sep 29, 2015 Issued
Array ( [id] => 12173771 [patent_doc_number] => 09891914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Method and apparatus for performing an efficient scatter' [patent_app_type] => utility [patent_app_number] => 14/684150 [patent_app_country] => US [patent_app_date] => 2015-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 14963 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14684150 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/684150
Method and apparatus for performing an efficient scatter Apr 9, 2015 Issued
Array ( [id] => 11042346 [patent_doc_number] => 20160239302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'DYNAMIC WAVEFRONT CREATION FOR PROCESSING UNITS USING A HYBRID COMPACTOR' [patent_app_type] => utility [patent_app_number] => 14/682971 [patent_app_country] => US [patent_app_date] => 2015-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5175 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14682971 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/682971
Dynamic wavefront creation for processing units using a hybrid compactor Apr 8, 2015 Issued
Array ( [id] => 11095013 [patent_doc_number] => 20160291981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'REMOVING INVALID LITERAL LOAD VALUES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA' [patent_app_type] => utility [patent_app_number] => 14/679408 [patent_app_country] => US [patent_app_date] => 2015-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8370 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14679408 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/679408
REMOVING INVALID LITERAL LOAD VALUES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA Apr 5, 2015 Abandoned
Array ( [id] => 11095159 [patent_doc_number] => 20160292127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word' [patent_app_type] => utility [patent_app_number] => 14/678939 [patent_app_country] => US [patent_app_date] => 2015-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14678939 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/678939
Low energy accelerator processor architecture with short parallel instruction word Apr 3, 2015 Issued
Array ( [id] => 13467153 [patent_doc_number] => 20180285119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => APPARATUS AND METHOD FOR INTER-STRAND COMMUNICATION [patent_app_type] => utility [patent_app_number] => 15/562408 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15562408 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/562408
APPARATUS AND METHOD FOR INTER-STRAND COMMUNICATION Mar 26, 2015 Abandoned
Array ( [id] => 16683266 [patent_doc_number] => 10942744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Systems, apparatuses, and methods for data speculation execution [patent_app_type] => utility [patent_app_number] => 14/582859 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 45 [patent_no_of_words] => 25277 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582859 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/582859
Systems, apparatuses, and methods for data speculation execution Dec 23, 2014 Issued
Array ( [id] => 11292488 [patent_doc_number] => 20160342420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'MECHANISM TO PRECLUDE SHARED RAM-DEPENDENT LOAD REPLAYS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/889270 [patent_app_country] => US [patent_app_date] => 2014-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10384 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14889270 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/889270
Mechanism to preclude shared RAM-dependent load replays in an out-of-order processor Dec 13, 2014 Issued
Array ( [id] => 13268925 [patent_doc_number] => 10146547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 14/889281 [patent_app_country] => US [patent_app_date] => 2014-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10043 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14889281 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/889281
Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor Dec 13, 2014 Issued
Array ( [id] => 13268923 [patent_doc_number] => 10146546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Load replay precluding mechanism [patent_app_type] => utility [patent_app_number] => 14/889223 [patent_app_country] => US [patent_app_date] => 2014-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9978 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14889223 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/889223
Load replay precluding mechanism Dec 13, 2014 Issued
Array ( [id] => 11314012 [patent_doc_number] => 20160350122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'APPARATUS AND METHOD TO PRECLUDE LOAD REPLAYS DEPENDENT ON WRITE COMBINING MEMORY SPACE ACCESS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/889339 [patent_app_country] => US [patent_app_date] => 2014-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10395 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14889339 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/889339
Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor Dec 13, 2014 Issued
Array ( [id] => 11314010 [patent_doc_number] => 20160350120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON LONG LOAD CYCLES IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/889243 [patent_app_country] => US [patent_app_date] => 2014-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10328 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14889243 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/889243
Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor Dec 13, 2014 Issued
Array ( [id] => 11314017 [patent_doc_number] => 20160350127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON OFF-DIE CONTROL ELEMENT ACCESS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/889306 [patent_app_country] => US [patent_app_date] => 2014-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10336 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14889306 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/889306
Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor Dec 13, 2014 Issued
Array ( [id] => 13948443 [patent_doc_number] => 10209996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Apparatus and method for programmable load replay preclusion [patent_app_type] => utility [patent_app_number] => 14/889358 [patent_app_country] => US [patent_app_date] => 2014-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10098 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14889358 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/889358
Apparatus and method for programmable load replay preclusion Dec 13, 2014 Issued
Array ( [id] => 11326956 [patent_doc_number] => 20160357568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON FUSE ARRAY ACCESS IN AN OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/889178 [patent_app_country] => US [patent_app_date] => 2014-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10345 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14889178 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/889178
Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor Dec 13, 2014 Issued
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