Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9745686 [patent_doc_number] => 20140281405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'OPTIMIZING PERFORMANCE FOR CONTEXT-DEPENDENT INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/841576 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5599 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13841576 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/841576
Optimizing performance for context-dependent instructions Mar 14, 2013 Issued
Array ( [id] => 9200352 [patent_doc_number] => 20130339667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION' [patent_app_type] => utility [patent_app_number] => 13/799670 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5537 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13799670 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/799670
SPECIAL CASE REGISTER UPDATE WITHOUT EXECUTION Mar 12, 2013
Array ( [id] => 11220461 [patent_doc_number] => 09448797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Restricted instructions in transactional execution' [patent_app_type] => utility [patent_app_number] => 13/783572 [patent_app_country] => US [patent_app_date] => 2013-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 30524 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783572 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/783572
Restricted instructions in transactional execution Mar 3, 2013 Issued
Array ( [id] => 9200388 [patent_doc_number] => 20130339703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'RESTRICTING PROCESSING WITHIN A PROCESSOR TO FACILITATE TRANSACTION COMPLETION' [patent_app_type] => utility [patent_app_number] => 13/783312 [patent_app_country] => US [patent_app_date] => 2013-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 32915 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783312 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/783312
Restricting processing within a processor to facilitate transaction completion Mar 2, 2013 Issued
Array ( [id] => 9200389 [patent_doc_number] => 20130339704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SAVING/RESTORING SELECTED REGISTERS IN TRANSACTIONAL PROCESSING' [patent_app_type] => utility [patent_app_number] => 13/783353 [patent_app_country] => US [patent_app_date] => 2013-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 28971 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783353 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/783353
Saving/restoring selected registers in transactional processing Mar 2, 2013 Issued
Array ( [id] => 9200390 [patent_doc_number] => 20130339705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'RANDOMIZED TESTING WITHIN TRANSACTIONAL EXECUTION' [patent_app_type] => utility [patent_app_number] => 13/783357 [patent_app_country] => US [patent_app_date] => 2013-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 30395 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783357 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/783357
Randomized testing within transactional execution Mar 2, 2013 Issued
Array ( [id] => 11563665 [patent_doc_number] => 09626256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Determining failure context in hardware transactional memories' [patent_app_type] => utility [patent_app_number] => 13/781658 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3152 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13781658 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/781658
Determining failure context in hardware transactional memories Feb 27, 2013 Issued
Array ( [id] => 11577520 [patent_doc_number] => 09632781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Vector register addressing and functions based on a scalar register data value' [patent_app_type] => utility [patent_app_number] => 13/777297 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7605 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777297 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/777297
Vector register addressing and functions based on a scalar register data value Feb 25, 2013 Issued
Array ( [id] => 9548980 [patent_doc_number] => 20140173627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'REQUESTING SHARED VARIABLE DIRECTORY (SVD) INFORMATION FROM A PLURALITY OF THREADS IN A PARALLEL COMPUTER' [patent_app_type] => utility [patent_app_number] => 13/766319 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13715 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766319 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766319
Requesting shared variable directory (SVD) information from a plurality of threads in a parallel computer Feb 12, 2013 Issued
Array ( [id] => 8855447 [patent_doc_number] => 20130145122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'INSTRUCTION PROCESSING METHOD OF NETWORK PROCESSOR AND NETWORK PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/763811 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5552 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13763811 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/763811
INSTRUCTION PROCESSING METHOD OF NETWORK PROCESSOR AND NETWORK PROCESSOR Feb 10, 2013 Abandoned
Array ( [id] => 11416598 [patent_doc_number] => 09563424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-07 [patent_title] => 'Native code instruction selection' [patent_app_type] => utility [patent_app_number] => 13/756371 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6180 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13756371 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/756371
Native code instruction selection Jan 30, 2013 Issued
Array ( [id] => 11584729 [patent_doc_number] => 09639371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Solution to divergent branches in a SIMD core using hardware pointers' [patent_app_type] => utility [patent_app_number] => 13/753113 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8276 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753113 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753113
Solution to divergent branches in a SIMD core using hardware pointers Jan 28, 2013 Issued
Array ( [id] => 9637076 [patent_doc_number] => 20140215185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'FETCHING INSTRUCTIONS OF A LOOP ROUTINE' [patent_app_type] => utility [patent_app_number] => 13/753380 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3656 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753380 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753380
FETCHING INSTRUCTIONS OF A LOOP ROUTINE Jan 28, 2013 Abandoned
Array ( [id] => 12932872 [patent_doc_number] => 09830164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Hardware and software solutions to divergent branches in a parallel pipeline [patent_app_type] => utility [patent_app_number] => 13/753098 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753098 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753098
Hardware and software solutions to divergent branches in a parallel pipeline Jan 28, 2013 Issued
Array ( [id] => 10976991 [patent_doc_number] => 20140380025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'MANAGEMENT OF HARDWARE ACCELERATOR CONFIGURATIONS IN A PROCESSOR CHIP' [patent_app_type] => utility [patent_app_number] => 14/123231 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9509 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14123231 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/123231
MANAGEMENT OF HARDWARE ACCELERATOR CONFIGURATIONS IN A PROCESSOR CHIP Jan 22, 2013 Abandoned
Array ( [id] => 8831663 [patent_doc_number] => 20130132708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 13/748132 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6755 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748132
MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD Jan 22, 2013 Abandoned
Array ( [id] => 11306512 [patent_doc_number] => 09513910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Requesting shared variable directory (SVD) information from a plurality of threads in a parallel computer' [patent_app_type] => utility [patent_app_number] => 13/718259 [patent_app_country] => US [patent_app_date] => 2012-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13683 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13718259 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/718259
Requesting shared variable directory (SVD) information from a plurality of threads in a parallel computer Dec 17, 2012 Issued
Array ( [id] => 11860815 [patent_doc_number] => 09740498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Opportunistic multi-thread method and processor' [patent_app_type] => utility [patent_app_number] => 14/357871 [patent_app_country] => US [patent_app_date] => 2012-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1836 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14357871 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/357871
Opportunistic multi-thread method and processor Nov 14, 2012 Issued
Array ( [id] => 10934585 [patent_doc_number] => 20140337606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'DIGITAL SIGNAL PROCESSOR, PROGRAM CONTROL METHOD, AND CONTROL PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/356816 [patent_app_country] => US [patent_app_date] => 2012-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9602 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14356816 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/356816
Digital signal processor, program control method, and control program Nov 1, 2012 Issued
Array ( [id] => 9451635 [patent_doc_number] => 20140122805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'SELECTIVE POISONING OF DATA DURING RUNAHEAD' [patent_app_type] => utility [patent_app_number] => 13/662171 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13662171 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/662171
Selective poisoning of data during runahead Oct 25, 2012 Issued
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