Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19084735 [patent_doc_number] => 20240111536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => DATA PROCESSING APPARATUS AND RELATED PRODUCTS [patent_app_type] => utility [patent_app_number] => 18/531734 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 77457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18531734 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/531734
Data processing apparatus and related products Dec 6, 2023 Issued
18/567544 THREAD TILING FOR MEMORY LATENCY REDUCTION Dec 5, 2023 Pending
Array ( [id] => 20403492 [patent_doc_number] => 12493465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Vector load store operations in a vector pipeline using a single operation in a load store unit [patent_app_type] => utility [patent_app_number] => 18/524222 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524222 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524222
Vector load store operations in a vector pipeline using a single operation in a load store unit Nov 29, 2023 Issued
Array ( [id] => 20034923 [patent_doc_number] => 20250173145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => FILTERING BRANCH INSTRUCTION PREDICTIONS [patent_app_type] => utility [patent_app_number] => 18/520983 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520983
FILTERING BRANCH INSTRUCTION PREDICTIONS Nov 27, 2023 Pending
Array ( [id] => 20017965 [patent_doc_number] => 20250156187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => REDUCTION OF DATA TRANSFER OVERHEAD [patent_app_type] => utility [patent_app_number] => 18/510088 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/510088
REDUCTION OF DATA TRANSFER OVERHEAD Nov 14, 2023 Issued
Array ( [id] => 19617370 [patent_doc_number] => 20240403050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => VECTOR COMPARISON AND/OR POPULATION COUNT OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/509121 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509121 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/509121
VECTOR COMPARISON AND/OR POPULATION COUNT OPERATIONS Nov 13, 2023 Pending
Array ( [id] => 20110052 [patent_doc_number] => 12360773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Thread commencement using a work descriptor packet in a self-scheduling processor [patent_app_type] => utility [patent_app_number] => 18/387045 [patent_app_country] => US [patent_app_date] => 2023-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 20020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18387045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/387045
Thread commencement using a work descriptor packet in a self-scheduling processor Nov 4, 2023 Issued
Array ( [id] => 19625635 [patent_doc_number] => 12164464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Multi-threaded, self-scheduling processor [patent_app_type] => utility [patent_app_number] => 18/386880 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 25246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/386880
Multi-threaded, self-scheduling processor Nov 2, 2023 Issued
Array ( [id] => 18974006 [patent_doc_number] => 20240054098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => FETCHING VECTOR DATA ELEMENTS WITH PADDING [patent_app_type] => utility [patent_app_number] => 18/496013 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18496013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/496013
Fetching vector data elements with padding Oct 26, 2023 Issued
Array ( [id] => 18973983 [patent_doc_number] => 20240054075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => NEURAL PROCESSING DEVICE AND LOAD/STORE METHOD OF NEURAL PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/494696 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494696 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494696
NEURAL PROCESSING DEVICE AND LOAD/STORE METHOD OF NEURAL PROCESSING DEVICE Oct 24, 2023 Pending
Array ( [id] => 18957348 [patent_doc_number] => 20240045675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => Apparatus for Calculating and Retaining a Bound on Error during Floating-Point Operations and Methods Thereof [patent_app_type] => utility [patent_app_number] => 18/492214 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/492214
Apparatus for Calculating and Retaining a Bound on Error during Floating-Point Operations and Methods Thereof Oct 22, 2023 Abandoned
Array ( [id] => 19878487 [patent_doc_number] => 20250110744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => BTB PREFECTHING VIA BACK-ANNOTATION [patent_app_type] => utility [patent_app_number] => 18/374363 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374363 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/374363
BTB PREFECTHING VIA BACK-ANNOTATION Sep 27, 2023 Issued
Array ( [id] => 18897302 [patent_doc_number] => 20240012787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/371635 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18371635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/371635
Multi-level hierarchical routing matrices for pattern-recognition processors Sep 21, 2023 Issued
Array ( [id] => 18998155 [patent_doc_number] => 11915003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Process parasitism-based branch prediction method and device for serverless computing, electronic device, and non-transitory readable storage medium [patent_app_type] => utility [patent_app_number] => 18/459397 [patent_app_country] => US [patent_app_date] => 2023-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4529 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459397 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/459397
Process parasitism-based branch prediction method and device for serverless computing, electronic device, and non-transitory readable storage medium Aug 30, 2023 Issued
Array ( [id] => 20460943 [patent_doc_number] => 20260010371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => PROCESSOR THAT IMPLEMENTS INDIRECT ADDRESSING-STYLE CONDITIONAL JUMP INSTRUCTIONS, PROGRAM RECORDING MEDIUM, AND METHOD [patent_app_type] => utility [patent_app_number] => 19/111422 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19111422 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/111422
PROCESSOR THAT IMPLEMENTS INDIRECT ADDRESSING-STYLE CONDITIONAL JUMP INSTRUCTIONS, PROGRAM RECORDING MEDIUM, AND METHOD Aug 24, 2023 Pending
Array ( [id] => 20564001 [patent_doc_number] => 12566610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Microprocessor with apparatus and method for replaying load instructions [patent_app_type] => utility [patent_app_number] => 18/237511 [patent_app_country] => US [patent_app_date] => 2023-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237511 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/237511
Microprocessor with apparatus and method for replaying load instructions Aug 23, 2023 Issued
Array ( [id] => 19669809 [patent_doc_number] => 12182568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Systems and methods for computing dot products of nibbles in two tile operands [patent_app_type] => utility [patent_app_number] => 18/449651 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 46 [patent_no_of_words] => 26156 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18449651 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/449651
Systems and methods for computing dot products of nibbles in two tile operands Aug 13, 2023 Issued
Array ( [id] => 19771995 [patent_doc_number] => 20250053421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => REGISTER CLEARING [patent_app_type] => utility [patent_app_number] => 18/448240 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448240 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448240
Register clearing Aug 10, 2023 Issued
Array ( [id] => 18912172 [patent_doc_number] => 11875151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-16 [patent_title] => Inter-process serving of machine learning features from mapped memory for machine learning models [patent_app_type] => utility [patent_app_number] => 18/359818 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4901 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359818 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359818
Inter-process serving of machine learning features from mapped memory for machine learning models Jul 25, 2023 Issued
Array ( [id] => 19747851 [patent_doc_number] => 20250036416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => Biased Indirect Control Transfer Prediction [patent_app_type] => utility [patent_app_number] => 18/358894 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358894 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358894
Biased indirect control transfer prediction Jul 24, 2023 Issued
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