Search

Thomas J. Mullen

Examiner (ID: 17198, Phone: (571)272-2965 , Office: P/2685 )

Most Active Art Unit
2685
Art Unit(s)
2612, 2685, 2632, 2787, 3616, 2617, 2736, 1724, 2608
Total Applications
2648
Issued Applications
2205
Pending Applications
106
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19905443 [patent_doc_number] => 12282448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Routing method based on a sorted operation unit graph for an iterative placement and routing on a reconfigurable processor [patent_app_type] => utility [patent_app_number] => 18/226010 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 18822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226010
Routing method based on a sorted operation unit graph for an iterative placement and routing on a reconfigurable processor Jul 24, 2023 Issued
Array ( [id] => 19633150 [patent_doc_number] => 20240411599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => CPU TIGHT-COUPLED ACCELERATOR [patent_app_type] => utility [patent_app_number] => 18/225041 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225041 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225041
CPU tight-coupled accelerator Jul 20, 2023 Issued
Array ( [id] => 19725824 [patent_doc_number] => 20250028575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => DATA PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/355282 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355282 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355282
DATA PROCESSING SYSTEM Jul 18, 2023 Pending
Array ( [id] => 19711196 [patent_doc_number] => 20250021338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => Next Fetch Predictor for Trace Cache [patent_app_type] => utility [patent_app_number] => 18/352326 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352326 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352326
Next fetch predictor for trace cache Jul 13, 2023 Issued
Array ( [id] => 19872960 [patent_doc_number] => 12265823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Trace cache with filter for internal control transfer inclusion [patent_app_type] => utility [patent_app_number] => 18/352323 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 19857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352323 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352323
Trace cache with filter for internal control transfer inclusion Jul 13, 2023 Issued
Array ( [id] => 19872966 [patent_doc_number] => 12265829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Re-triggering wake-up to handle time skew between scalar and vector sides [patent_app_type] => utility [patent_app_number] => 18/338643 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338643 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/338643
Re-triggering wake-up to handle time skew between scalar and vector sides Jun 20, 2023 Issued
Array ( [id] => 18711270 [patent_doc_number] => 20230333899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => ACCELERATOR, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/337723 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337723 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337723
Accelerator, method of operating the same, and electronic device including the same Jun 19, 2023 Issued
Array ( [id] => 19963800 [patent_doc_number] => 12333309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Differential pipeline delays in a coprocessor [patent_app_type] => utility [patent_app_number] => 18/211007 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211007
Differential pipeline delays in a coprocessor Jun 15, 2023 Issued
Array ( [id] => 20494150 [patent_doc_number] => 12536019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => FPGA wide barrel-shifters implementation using packed DSP multipliers [patent_app_type] => utility [patent_app_number] => 18/335127 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 4363 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/335127
FPGA wide barrel-shifters implementation using packed DSP multipliers Jun 13, 2023 Issued
Array ( [id] => 19633269 [patent_doc_number] => 20240411718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => HARDWARE-BASED IMAGE/VIDEO PROCESSING IN MACHINE LEARNING-ACCELERATOR SYSTEM-ON-CHIP [patent_app_type] => utility [patent_app_number] => 18/333377 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333377
Hardware-based image/video processing in machine learning-accelerator system-on-chip Jun 11, 2023 Issued
Array ( [id] => 19022141 [patent_doc_number] => 20240078312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => Simultaneous Multi-Processor (SiMulPro) Apparatus, Simultaneous Transmit And Receive (STAR) Apparatus, DRAM Interface Apparatus, and Associated Methods [patent_app_type] => utility [patent_app_number] => 18/206188 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206188 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206188
Simultaneous Multi-Processor (SiMulPro) Apparatus, Simultaneous Transmit And Receive (STAR) Apparatus, DRAM Interface Apparatus, and Associated Methods Jun 5, 2023 Abandoned
Array ( [id] => 19617372 [patent_doc_number] => 20240403052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => INDEXED VECTOR PERMUTATION OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/329456 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329456
INDEXED VECTOR PERMUTATION OPERATIONS Jun 4, 2023 Pending
Array ( [id] => 19942625 [patent_doc_number] => 12314757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-27 [patent_title] => Efficient resource scheduling using adaptive scheduling criteria [patent_app_type] => utility [patent_app_number] => 18/205702 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5792 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205702 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205702
Efficient resource scheduling using adaptive scheduling criteria Jun 4, 2023 Issued
Array ( [id] => 20446908 [patent_doc_number] => 20260003630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => PROCESSOR FOR CONTROLLING PIPELINE PROCESSING BASED ON JUMP INSTRUCTION, AND PROGRAM STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/876798 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18876798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/876798
PROCESSOR FOR CONTROLLING PIPELINE PROCESSING BASED ON JUMP INSTRUCTION, AND PROGRAM STORAGE MEDIUM May 29, 2023 Pending
Array ( [id] => 19190002 [patent_doc_number] => 20240168915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => Graph Spatial Split [patent_app_type] => utility [patent_app_number] => 18/202059 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202059
Graph spatial split May 24, 2023 Issued
Array ( [id] => 20415646 [patent_doc_number] => 12498931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Preserving memory ordering between offloaded instructions and non-offloaded instructions [patent_app_type] => utility [patent_app_number] => 18/298723 [patent_app_country] => US [patent_app_date] => 2023-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298723 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/298723
Preserving memory ordering between offloaded instructions and non-offloaded instructions Apr 10, 2023 Issued
Array ( [id] => 18539812 [patent_doc_number] => 20230244920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => NEURAL PROCESSING DEVICE AND METHOD FOR SYNCHRONIZATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/298935 [patent_app_country] => US [patent_app_date] => 2023-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/298935
Neural processing device and method for synchronization thereof Apr 10, 2023 Issued
Array ( [id] => 19481949 [patent_doc_number] => 20240329991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => INSTRUCTIONS FOR FLOATING POINT MULTIPLICATION AND ADDITION AND CONVERSION EMPLOYING VARIABLE PRECISION [patent_app_type] => utility [patent_app_number] => 18/194327 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194327 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/194327
INSTRUCTIONS FOR FLOATING POINT MULTIPLICATION AND ADDITION AND CONVERSION EMPLOYING VARIABLE PRECISION Mar 30, 2023 Pending
Array ( [id] => 20221567 [patent_doc_number] => 20250284498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => INTERRUPT CONTROLLER, APPARATUS, INTERRUPT CONTROL METHOD AND COMPUTER-READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/861990 [patent_app_country] => US [patent_app_date] => 2023-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18861990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/861990
INTERRUPT CONTROLLER, APPARATUS, INTERRUPT CONTROL METHOD AND COMPUTER-READABLE MEDIUM Mar 27, 2023 Pending
Array ( [id] => 18531762 [patent_doc_number] => 20230236834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING 16-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/190761 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190761 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190761
Systems and methods for performing 16-bit floating-point matrix dot product instructions Mar 26, 2023 Issued
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