Thomas J Visone
Examiner (ID: 14957, Phone: (571)270-7144 , Office: P/1651 )
Most Active Art Unit | 1651 |
Art Unit(s) | 1651, 1699, 4112 |
Total Applications | 539 |
Issued Applications | 253 |
Pending Applications | 58 |
Abandoned Applications | 228 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1276745
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[patent_issue_date] => 2003-11-25
[patent_title] => 'Systems and methods for wireless communications'
[patent_app_type] => B1
[patent_app_number] => 09/231335
[patent_app_country] => US
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[pdf_file] => patents/06/654/06654428.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/231335 | Systems and methods for wireless communications | Jan 12, 1999 | Issued |
Array
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[patent_kind] => B1
[patent_issue_date] => 2002-08-20
[patent_title] => 'Method and apparatus for a digitally controlled constant current source for phase adjustment of a synthesized clock'
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[patent_app_number] => 09/228451
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/228451 | Method and apparatus for a digitally controlled constant current source for phase adjustment of a synthesized clock | Jan 10, 1999 | Issued |
Array
(
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[patent_doc_number] => 06434184
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[patent_issue_date] => 2002-08-13
[patent_title] => 'Orthogonal frequency hopping using skip zones'
[patent_app_type] => B1
[patent_app_number] => 09/223680
[patent_app_country] => US
[patent_app_date] => 1998-12-30
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Array
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[patent_title] => 'Symbol alignment method'
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Array
(
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[patent_title] => 'Apparatus and method for broadcast band noise reduction in a transmitter with a low IF frequency'
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[patent_app_number] => 09/212903
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Array
(
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[patent_title] => 'Sign-cross product automatic frequency control loop'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/212625 | Sign-cross product automatic frequency control loop | Dec 15, 1998 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/210424 | Synchronization and clock recovery | Dec 10, 1998 | Issued |
Array
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[id] => 1570844
[patent_doc_number] => 06377647
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[patent_title] => 'PLL circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205804 | PLL circuit | Dec 3, 1998 | Issued |
Array
(
[id] => 6705437
[patent_doc_number] => 20030152171
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[patent_issue_date] => 2003-08-14
[patent_title] => 'METHOD FOR INITIALIZING A VITERBI DECODER IN FRAMED MODE'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205600 | METHOD FOR INITIALIZING A VITERBI DECODER IN FRAMED MODE | Dec 3, 1998 | Abandoned |
Array
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[id] => 1320525
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[patent_issue_date] => 2003-09-02
[patent_title] => 'System and method of communication via embedded modulation'
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[patent_app_number] => 09/205205
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205205 | System and method of communication via embedded modulation | Dec 3, 1998 | Issued |
Array
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[patent_title] => 'Decoding of a biphase modulated bitstream and relative self-synchronizing frequency divider with noninteger ratio'
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Array
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[id] => 4343874
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Array
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Array
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Array
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Array
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Array
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