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Thomas Kaleikaumaka Wong

Examiner (ID: 7450)

Most Active Art Unit
4186
Art Unit(s)
4186
Total Applications
13
Issued Applications
0
Pending Applications
13
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 673653 [patent_doc_number] => 07091891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Calibration of analog to digital converter by means of multiplexed stages' [patent_app_type] => utility [patent_app_number] => 10/833774 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4981 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/091/07091891.pdf [firstpage_image] =>[orig_patent_app_number] => 10833774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/833774
Calibration of analog to digital converter by means of multiplexed stages Apr 27, 2004 Issued
Array ( [id] => 730848 [patent_doc_number] => 07042251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Multi-function differential logic gate' [patent_app_type] => utility [patent_app_number] => 10/833398 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7498 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/042/07042251.pdf [firstpage_image] =>[orig_patent_app_number] => 10833398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/833398
Multi-function differential logic gate Apr 27, 2004 Issued
Array ( [id] => 780224 [patent_doc_number] => 06995703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Analog-to-digital converting circuit and image processing circuit cyclically repeating AD conversion' [patent_app_type] => utility [patent_app_number] => 10/831270 [patent_app_country] => US [patent_app_date] => 2004-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9544 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/995/06995703.pdf [firstpage_image] =>[orig_patent_app_number] => 10831270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/831270
Analog-to-digital converting circuit and image processing circuit cyclically repeating AD conversion Apr 25, 2004 Issued
Array ( [id] => 6950370 [patent_doc_number] => 20050225464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Current switching arrangement for D.A.C. reconstruction filtering' [patent_app_type] => utility [patent_app_number] => 10/821576 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20050225464.pdf [firstpage_image] =>[orig_patent_app_number] => 10821576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821576
Current switching arrangement for D.A.C. reconstruction filtering Apr 8, 2004 Issued
Array ( [id] => 6950374 [patent_doc_number] => 20050225468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Subranging analog-to-digital converter with integrating sample-and-hold' [patent_app_type] => utility [patent_app_number] => 10/821376 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20050225468.pdf [firstpage_image] =>[orig_patent_app_number] => 10821376 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821376
Subranging analog-to-digital converter with integrating sample-and-hold Apr 7, 2004 Issued
Array ( [id] => 964235 [patent_doc_number] => 06950048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-27 [patent_title] => 'Dither system for a quantizing device' [patent_app_type] => utility [patent_app_number] => 10/817477 [patent_app_country] => US [patent_app_date] => 2004-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2019 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950048.pdf [firstpage_image] =>[orig_patent_app_number] => 10817477 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/817477
Dither system for a quantizing device Apr 1, 2004 Issued
Array ( [id] => 7196968 [patent_doc_number] => 20040205447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same' [patent_app_type] => new [patent_app_number] => 10/815505 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14275 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20040205447.pdf [firstpage_image] =>[orig_patent_app_number] => 10815505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815505
Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same Mar 31, 2004 Issued
Array ( [id] => 994261 [patent_doc_number] => 06917319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-12 [patent_title] => 'Digital to analog converter using tunneling current element' [patent_app_type] => utility [patent_app_number] => 10/708877 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917319.pdf [firstpage_image] =>[orig_patent_app_number] => 10708877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708877
Digital to analog converter using tunneling current element Mar 29, 2004 Issued
Array ( [id] => 1000200 [patent_doc_number] => 06911926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'D/A conversion circuit and semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/810573 [patent_app_country] => US [patent_app_date] => 2004-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 57 [patent_no_of_words] => 29395 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/911/06911926.pdf [firstpage_image] =>[orig_patent_app_number] => 10810573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/810573
D/A conversion circuit and semiconductor device Mar 28, 2004 Issued
Array ( [id] => 7017065 [patent_doc_number] => 20050219083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Architecture for bidirectional serializers and deserializer' [patent_app_type] => utility [patent_app_number] => 10/802372 [patent_app_country] => US [patent_app_date] => 2004-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20050219083.pdf [firstpage_image] =>[orig_patent_app_number] => 10802372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/802372
Architecture for bidirectional serializers and deserializer Mar 15, 2004 Abandoned
Array ( [id] => 7399516 [patent_doc_number] => 20040174941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Apparatus and method for decoding' [patent_app_type] => new [patent_app_number] => 10/793766 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15519 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20040174941.pdf [firstpage_image] =>[orig_patent_app_number] => 10793766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/793766
Apparatus and method for decoding Mar 7, 2004 Issued
Array ( [id] => 969150 [patent_doc_number] => 06940428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Apparatus and method for decoding' [patent_app_type] => utility [patent_app_number] => 10/793737 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 15444 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940428.pdf [firstpage_image] =>[orig_patent_app_number] => 10793737 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/793737
Apparatus and method for decoding Mar 7, 2004 Issued
Array ( [id] => 1110005 [patent_doc_number] => 06809677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'Analog to digital converter selecting reference voltages in accordance with feedback from prior stages' [patent_app_type] => B2 [patent_app_number] => 10/788290 [patent_app_country] => US [patent_app_date] => 2004-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4479 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/809/06809677.pdf [firstpage_image] =>[orig_patent_app_number] => 10788290 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/788290
Analog to digital converter selecting reference voltages in accordance with feedback from prior stages Feb 29, 2004 Issued
Array ( [id] => 1022929 [patent_doc_number] => 06888424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Piezoelectric resonator, filter, and electronic communication device' [patent_app_type] => utility [patent_app_number] => 10/785284 [patent_app_country] => US [patent_app_date] => 2004-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4411 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888424.pdf [firstpage_image] =>[orig_patent_app_number] => 10785284 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/785284
Piezoelectric resonator, filter, and electronic communication device Feb 23, 2004 Issued
Array ( [id] => 7324279 [patent_doc_number] => 20040252037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'D/A converting device with offset compensation function and offset compensation method for D/A converting device' [patent_app_type] => new [patent_app_number] => 10/782873 [patent_app_country] => US [patent_app_date] => 2004-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8236 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20040252037.pdf [firstpage_image] =>[orig_patent_app_number] => 10782873 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/782873
D/A converting device with offset compensation function and offset compensation method for D/A converting device Feb 22, 2004 Abandoned
Array ( [id] => 7273630 [patent_doc_number] => 20040233081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Analog-to-digital converter with correction of offset errors' [patent_app_type] => new [patent_app_number] => 10/781570 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5410 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233081.pdf [firstpage_image] =>[orig_patent_app_number] => 10781570 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781570
Analog-to-digital converter with correction of offset errors Feb 17, 2004 Issued
Array ( [id] => 709382 [patent_doc_number] => 07061415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Word length reduction circuit' [patent_app_type] => utility [patent_app_number] => 10/777763 [patent_app_country] => US [patent_app_date] => 2004-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7255 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061415.pdf [firstpage_image] =>[orig_patent_app_number] => 10777763 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/777763
Word length reduction circuit Feb 12, 2004 Issued
Array ( [id] => 1000192 [patent_doc_number] => 06911923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'Data realignment techniques for serial-to-parallel conversion' [patent_app_type] => utility [patent_app_number] => 10/769733 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3051 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/911/06911923.pdf [firstpage_image] =>[orig_patent_app_number] => 10769733 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/769733
Data realignment techniques for serial-to-parallel conversion Jan 28, 2004 Issued
Array ( [id] => 7037331 [patent_doc_number] => 20050156765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Clocked D/A converter' [patent_app_type] => utility [patent_app_number] => 10/763071 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3636 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156765.pdf [firstpage_image] =>[orig_patent_app_number] => 10763071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/763071
Clocked D/A converter Jan 20, 2004 Issued
Array ( [id] => 1023068 [patent_doc_number] => 06888482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Folding analog to digital converter capable of calibration and method thereof' [patent_app_type] => utility [patent_app_number] => 10/707861 [patent_app_country] => US [patent_app_date] => 2004-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3772 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888482.pdf [firstpage_image] =>[orig_patent_app_number] => 10707861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707861
Folding analog to digital converter capable of calibration and method thereof Jan 18, 2004 Issued
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